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| Cyclone Device Handbook, Volume 1 Preliminary Information 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com C5V1-1.0 Copyright (c) 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Printed on recycled paper ii Preliminary Altera Corporation Contents Chapter Revision Dates ........................................................................... xi About this Handbook ............................................................................. xiii How to Find Information ..................................................................................................................... xiii How to Contact Altera .......................................................................................................................... xiii Typographic Conventions .................................................................................................................... xiv Section I. Cyclone FPGA Family Data Sheet Revision History ....................................................................................................................... Section I-1 Chapter 1. Introduction Introduction ............................................................................................................................................ 1-1 Features ................................................................................................................................................... 1-2 Chapter 2. Cyclone Architecture Functional Description .......................................................................................................................... 2-1 Logic Array Blocks ................................................................................................................................ 2-3 LAB Interconnects ............................................................................................................................ 2-3 LAB Control Signals ......................................................................................................................... 2-4 Logic Elements ....................................................................................................................................... 2-5 LUT Chain & Register Chain .......................................................................................................... 2-7 addnsub Signal ................................................................................................................................. 2-7 LE Operating Modes ........................................................................................................................ 2-7 MultiTrack Interconnect ..................................................................................................................... 2-12 Embedded Memory ............................................................................................................................. 2-18 Memory Modes ............................................................................................................................... 2-18 Parity Bit Support ........................................................................................................................... 2-20 Shift Register Support .................................................................................................................... 2-20 Memory Configuration Sizes ........................................................................................................ 2-21 Byte Enables .................................................................................................................................... 2-23 Control Signals & M4K Interface ................................................................................................. 2-23 Independent Clock Mode .............................................................................................................. 2-25 Input/Output Clock Mode ........................................................................................................... 2-25 Read/Write Clock Mode ............................................................................................................... 2-27 Single-Port Mode ............................................................................................................................ 2-28 Global Clock Network & Phase-Locked Loops ............................................................................... 2-29 Global Clock Network ................................................................................................................... 2-29 Dual-Purpose Clock Pins .............................................................................................................. 2-30 Altera Corporation iii Preliminary Cyclone Device Handbook, Volume 1 Combined Resources ..................................................................................................................... PLLs .................................................................................................................................................. Clock Multiplication & Division .................................................................................................. External Clock Inputs .................................................................................................................... External Clock Outputs ................................................................................................................. Clock Feedback ............................................................................................................................... Phase Shifting ................................................................................................................................. Lock Detect Signal .......................................................................................................................... Programmable Duty Cycle ........................................................................................................... Control Signals ................................................................................................................................ I/O Structure ........................................................................................................................................ External RAM Interfacing ............................................................................................................. DDR SDRAM & FCRAM .............................................................................................................. Programmable Drive Strength ..................................................................................................... Open-Drain Output ........................................................................................................................ Slew-Rate Control .......................................................................................................................... Bus Hold .......................................................................................................................................... Programmable Pull-Up Resistor .................................................................................................. Advanced I/O Standard Support ................................................................................................ LVDS I/O Pins ................................................................................................................................ MultiVolt I/O Interface ................................................................................................................. Power Sequencing & Hot Socketing ................................................................................................. 2-31 2-32 2-35 2-36 2-36 2-37 2-37 2-37 2-38 2-38 2-39 2-46 2-46 2-49 2-50 2-50 2-51 2-51 2-52 2-54 2-54 2-55 Chapter 3. Configuration & Testing IEEE Std. 1149.1 (JTAG) Boundary Scan Support ............................................................................. SignalTap II Embedded Logic Analyzer ............................................................................................ Configuration ......................................................................................................................................... Operating Modes .............................................................................................................................. Configuration Schemes ................................................................................................................... 3-1 3-5 3-5 3-6 3-6 Chapter 4. DC & Switching Characteristics Operating Conditions ........................................................................................................................... 4-1 Power Consumption ............................................................................................................................. 4-8 Timing Model ......................................................................................................................................... 4-9 Preliminary & Final Timing ............................................................................................................ 4-9 Internal Timing Parameters .......................................................................................................... 4-10 External Timing Parameters ......................................................................................................... 4-14 External I/O Delay Parameters .................................................................................................... 4-21 Maximum Input & Output Clock Rates ...................................................................................... 4-27 Chapter 5. Reference & Ordering Information Software .................................................................................................................................................. 5-1 Device Pin-Outs ..................................................................................................................................... 5-1 Ordering Information ........................................................................................................................... 5-1 1-iv Preliminary Altera Corporation Contents Section II. Clock Management Revision History ..................................................................................................................... Section II-1 Chapter 6. Using PLLs in Cyclone Devices Introduction ............................................................................................................................................ 6-1 Hardware Overview ........................................................................................................................ 6-1 Software Overview .......................................................................................................................... 6-4 Pins & Clock Network Connections .............................................................................................. 6-6 Hardware Features ................................................................................................................................ 6-8 Clock Multiplication & Division .................................................................................................... 6-8 Phase Shifting ................................................................................................................................... 6-9 Programmable Duty Cycle ........................................................................................................... 6-10 External Clock Output ................................................................................................................... 6-11 Control Signals ................................................................................................................................ 6-12 Clock Feedback Modes ....................................................................................................................... 6-13 Normal Mode .................................................................................................................................. 6-13 Zero Delay Buffer Mode ................................................................................................................ 6-14 No Compensation .......................................................................................................................... 6-15 Pins ......................................................................................................................................................... 6-16 Board Layout ........................................................................................................................................ 6-17 VCCA & GNDA ............................................................................................................................. 6-17 Jitter Considerations ...................................................................................................................... 6-19 Specifications ........................................................................................................................................ 6-20 Software Support ................................................................................................................................. 6-21 Quartus II altpll Megafunction ..................................................................................................... 6-21 altpll Input Ports ............................................................................................................................. 6-22 altpll Output Ports ......................................................................................................................... 6-23 MegaWizard Customization ......................................................................................................... 6-23 MegaWizard Page Description ..................................................................................................... 6-25 Compilation Report ....................................................................................................................... 6-31 Timing Analysis .............................................................................................................................. 6-33 Simulation ....................................................................................................................................... 6-37 Global Clock Network ........................................................................................................................ 6-38 Dedicated Clock Input Pins .......................................................................................................... 6-40 Dual-Purpose Clock I/O Pins ...................................................................................................... 6-40 Combined Sources .......................................................................................................................... 6-41 Conclusion ............................................................................................................................................ 6-43 Section III. Memory Revision History .................................................................................................................... Section III-1 Chapter 7. On-Chip Memory Implementations Using Cyclone Memory Blocks Introduction ............................................................................................................................................ 7-1 M4K Memory Features ......................................................................................................................... 7-1 Altera Corporation 1-v Preliminary Cyclone Device Handbook, Volume 1 Parity Bit Support ............................................................................................................................. 7-2 Byte-Enable Support ........................................................................................................................ 7-3 Power-up Conditions & Memory Initialization ........................................................................... 7-4 Using M4K Memory .............................................................................................................................. 7-4 Implementing Single-Port Mode .................................................................................................... 7-5 Implementing Simple Dual-Port Mode ......................................................................................... 7-6 Implementing True Dual-Port Mode ............................................................................................ 7-8 Implementing Shift-Register Mode ............................................................................................. 7-11 Implementing ROM Mode ............................................................................................................ 7-12 Implementing FIFO Buffers .......................................................................................................... 7-12 Clock Modes ......................................................................................................................................... 7-13 Independent Clock Mode .............................................................................................................. 7-13 Input/Output Clock Mode ........................................................................................................... 7-15 Read/Write Clock Mode ............................................................................................................... 7-17 Single-Port Mode ............................................................................................................................ 7-18 Synchronous & Pseudo-Asynchronous Modes ............................................................................... 7-19 Read-during-Write Operation at the Same Address ...................................................................... 7-20 Same-Port Read-during-Write Mode .......................................................................................... 7-20 Mixed-Port Read-during-Write Mode ........................................................................................ 7-21 Conclusion ............................................................................................................................................ 7-23 Section IV. I/O Standards Revision History .................................................................................................................... Section IV-1 Chapter 8. Using Selectable I/O Standards in Cyclone Devices Introduction ............................................................................................................................................ 8-1 Supported I/O Standards ..................................................................................................................... 8-2 3.3-V LVTTL (EIA/JEDEC Standard JESD8-B) ............................................................................ 8-2 3.3-V LVCMOS (EIA/JEDEC Standard JESD8-B) ....................................................................... 8-3 2.5-V LVTTL Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-5) ......... 8-3 2.5-V LVCMOS Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-5) .... 8-4 1.8-V LVTTL Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-7) ......... 8-4 1.8-V LVCMOS Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-7) .... 8-4 1.5-V LVCMOS Normal & Wide Voltage Ranges (EIA/JEDEC Standard JESD8-11) ............ 8-5 3.3-V (PCI Special Interest Group (SIG) PCI Local Bus Specification Revision 2.2) ............... 8-5 SSTL-3 Class I & II (EIA/JEDEC Standard JESD8-8) .................................................................. 8-5 SSTL-2 Class I & II (EIA/JEDEC Standard JESD8-9A) ............................................................... 8-6 LVDS (ANSI/TIA/EIA Standard ANSI/TIA/EIA-644) ............................................................ 8-7 Differential SSTL-2 - EIA/JEDEC Standard JESD8-9A ............................................................... 8-8 Cyclone I/O Banks ................................................................................................................................ 8-8 Programmable Current Drive Strength ............................................................................................ 8-11 Hot Socketing ....................................................................................................................................... 8-12 I/O Termination .................................................................................................................................. 8-12 Voltage-Referenced I/O Standard Termination ........................................................................ 8-13 Differential I/O Standard Termination ...................................................................................... 8-13 1-vi Preliminary Altera Corporation Contents Pad Placement & DC Guidelines ....................................................................................................... Differential Pad Placement Guidelines ....................................................................................... VREF Pad Placement Guidelines ................................................................................................... DC Guidelines ................................................................................................................................. Quartus II Software Support .............................................................................................................. Compiler Settings ........................................................................................................................... Conclusion ............................................................................................................................................ More Information ................................................................................................................................ References ............................................................................................................................................. 8-13 8-13 8-13 8-16 8-17 8-17 8-20 8-21 8-21 Chapter 9. Implementing LVDS in Cyclone Devices Introduction ............................................................................................................................................ 9-1 Cyclone LVDS I/O Banks ..................................................................................................................... 9-1 Cyclone LVDS I/O Interface ................................................................................................................ 9-3 Clock Domains .................................................................................................................................. 9-3 LVDS Receiver & Transmitter ........................................................................................................ 9-4 LVDS Timing in Cyclone Devices .................................................................................................. 9-7 Cyclone Receiver & Transmitter Termination ................................................................................... 9-8 Implementing Cyclone LVDS I/O Pins in the Quartus II Software ............................................ 9-10 Transmitting Serial Data on Cyclone LVDS Outputs ............................................................... 9-10 Capturing Serial Data on Cyclone LVDS Inputs ....................................................................... 9-14 Design Guidelines ............................................................................................................................... 9-16 Differential Pad Placement Guidelines ....................................................................................... 9-17 Board Design Considerations ....................................................................................................... 9-17 Conclusion ............................................................................................................................................ 9-18 Section V. Design Considerations Revision History ..................................................................................................................... Section V-1 Chapter 10. Implementing Double Data Rate I/O Signaling in Cyclone Devices Introduction .......................................................................................................................................... Double Data Rate Input ...................................................................................................................... Double Data Rate Output ................................................................................................................... Bidirectional Double Data Rate ......................................................................................................... DDR Memory Support ........................................................................................................................ Conclusion ............................................................................................................................................ 10-1 10-1 10-2 10-3 10-4 10-4 Chapter 11. Using Cyclone Devices in Multiple-Voltage Systems Introduction .......................................................................................................................................... I/O Standards ...................................................................................................................................... MultiVolt I/O Operation .................................................................................................................... 5.0-V Device Compatibility ................................................................................................................ Hot-Socketing ....................................................................................................................................... Devices Can Be Driven before Power-Up ................................................................................... I/O Pins Remain Tri-Stated during Power-Up .......................................................................... 11-1 11-1 11-2 11-3 11-6 11-6 11-6 Altera Corporation 1-vii Preliminary Cyclone Device Handbook, Volume 1 Signal Pins Do Not Drive the VCCIO or VCCINT Power Supplies .............................................. Power-Up Sequence ............................................................................................................................ Power-On Reset ................................................................................................................................... Conclusion ............................................................................................................................................ 11-6 11-7 11-7 11-8 Chapter 12. Designing with 1.5-V Devices Introduction .......................................................................................................................................... 12-1 Power Sequencing & Hot Socketing ................................................................................................. 12-1 Using MultiVolt I/O Pins ................................................................................................................... 12-2 Voltage Regulators .............................................................................................................................. 12-3 Linear Voltage Regulators ............................................................................................................. 12-4 Switching Voltage Regulators ...................................................................................................... 12-6 Maximum Output Current ........................................................................................................... 12-8 Selecting Voltage Regulators ........................................................................................................ 12-8 Voltage Divider Network ............................................................................................................ 12-10 1.5-V Regulator Circuits .............................................................................................................. 12-10 1.5-V Regulator Application Examples .......................................................................................... 12-19 Synchronous Switching Regulator Example ............................................................................ 12-20 Board Layout ...................................................................................................................................... 12-21 Split-Plane Method ....................................................................................................................... 12-23 Conclusion .......................................................................................................................................... 12-23 References ........................................................................................................................................... 12-24 Section VI. Configuration Revision History .................................................................................................................... Section VI-1 Chapter 13. Configuring Cyclone FPGAs Introduction .......................................................................................................................................... 13-1 Device Configuration Overview ....................................................................................................... 13-1 Data Compression ............................................................................................................................... 13-3 Configuration Schemes ....................................................................................................................... 13-6 Active Serial Configuration (Serial Configuration Devices) .................................................... 13-7 Passive Serial Configuration ....................................................................................................... 13-13 JTAG-Based Configuration ......................................................................................................... 13-25 Combining Configuration Schemes ................................................................................................ 13-39 Active Serial & JTAG ................................................................................................................... 13-39 Passive Serial & JTAG .................................................................................................................. 13-40 Device Options ................................................................................................................................... 13-41 Device Configuration Pins ............................................................................................................... 13-45 Device Configuration Files ............................................................................................................... 13-47 SRAM Object File (.sof) ............................................................................................................... 13-47 Programmer Object File (.pof) .................................................................................................... 13-48 Raw Binary File (.rbf) ................................................................................................................... 13-48 Hexadecimal (Intel-Format) File (.hex) ..................................................................................... 13-48 Tabular Text File (.ttf) .................................................................................................................. 13-48 1-viii Preliminary Altera Corporation Contents Jam File (.jam) ............................................................................................................................... Jam Byte-Code File (.jbc) ............................................................................................................. Configuration Reliability .................................................................................................................. Board Layout Tips ............................................................................................................................. 13-49 13-49 13-49 13-50 Chapter 14. Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet Features ................................................................................................................................................. 14-1 Functional Description ........................................................................................................................ 14-2 Accessing Memory in Serial Configuration Devices ...................................................................... 14-3 Pin Description ..................................................................................................................................... 14-4 Programming & Configuration File Support .................................................................................. 14-4 Cyclone FPGA Configuration ............................................................................................................ 14-7 Power & Operation ............................................................................................................................ 14-11 Power Mode .................................................................................................................................. 14-11 Power-On Reset ............................................................................................................................ 14-11 Error Detection ............................................................................................................................. 14-11 Operating Conditions ....................................................................................................................... 14-12 Package ................................................................................................................................................ 14-13 Ordering Code ................................................................................................................................... 14-14 Index Altera Corporation 1-ix Preliminary Cyclone Device Handbook, Volume 1 1-x Preliminary Altera Corporation Chapter Revision Dates The chapters in this book, Cyclone Device Handbook, Volume 1, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. Introduction Revised: Part number: May 2003 C51001-1.0 Chapter 2. Cyclone Architecture Revised: May 2003 Part number: C51002-1.0 Chapter 3. Configuration & Testing Revised: May 2003 Part number: C51003-1.0 Chapter 4. DC & Switching Characteristics Revised: May 2003 Part number: C51004-1.0 Chapter 5. Reference & Ordering Information Revised: May 2003 Part number: C51005-1.0 Chapter 6. Using PLLs in Cyclone Devices Revised: May 2003 Part number: C51006-1.0 Chapter 7. On-Chip Memory Implementations Using Cyclone Memory Blocks Revised: May 2003 Part number: C51007-1.0 Chapter 8. Using Selectable I/O Standards in Cyclone Devices Revised: May 2003 Part number: C51008-1.0 Chapter 9. Implementing LVDS in Cyclone Devices Revised: May 2003 Part number: C51009-1.0 Altera Corporation xi Preliminary Cyclone Device Handbook, Volume 1 Chapter 10. Implementing Double Data Rate I/O Signaling in Cyclone Devices Revised: May 2003 Part number: C51010-1.0 Chapter 11. Using Cyclone Devices in Multiple-Voltage Systems Revised: May 2003 Part number: C51011-1.0 Chapter 12. Designing with 1.5-V Devices Revised: May 2003 Part number: C51012-1.0 Chapter 13. Configuring Cyclone FPGAs Revised: May 2003 Part number: C51013-1.0 Chapter 14. Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet Revised: May 2003 Part number: C51014-1.0 1-xii Preliminary Altera Corporation About this Handbook This handbook provides comprehensive information about the Altera(R) CycloneTM family of devices. How to Find Information You can find more information in the following ways: The Adobe Acrobat Find feature, which searches the text of a PDF document. Click the binoculars toolbar icon to open the Find dialog box. Acrobat bookmarks, which serve as an additional table of contents in PDF documents. Thumbnail icons, which provide miniature previews of each page, provide a link to the pages. Numerous links, shown in green text, which allow you to jump to related information. How to Contact Altera Information Type Technical support For the most up-to-date information about Altera products, go to the Altera world-wide web site at www.altera.com. For technical support on this product, go to www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below. USA & Canada www.altera.com/mysupport/ (800) 800-EPLD (3753) (7:00 a.m. to 5:00 p.m. Pacific Time) All Other Locations www.altera.com/mysupport/ (408) 544-7000 (1) (7:00 a.m. to 5:00 p.m. Pacific Time) www.altera.com lit_req@altera.com (1) (408) 544-7000 (7:30 a.m. to 5:30 p.m. Pacific Time) ftp.altera.com Product literature Altera literature services Non-technical customer service FTP site Note to table: (1) www.altera.com lit_req@altera.com (1) (800) 767-3753 ftp.altera.com You can also contact your local Altera sales office or sales representative. Altera Corporation xiii Preliminary Cyclone Device Handbook, Volume 1 Typographic Conventions Visual Cue Bold Type with Initial Capital Letters bold type This document uses the typographic conventions shown below. Meaning Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file. Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design. Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: Italic Type with Initial Capital Letters Italic type Initial Capital Letters "Subheading Title" Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: "Typographic Conventions." Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier. Courier type 1., 2., 3., and a., b., c., etc. v 1 r f Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets are used in a list of items when the sequence of the items is not important. The checkmark indicates a procedure that consists of one step only. The hand points to information that requires special attention. The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. * 1-xiv Preliminary Altera Corporation Section I. Cyclone FPGA Family Data Sheet This section provides designers with the data sheet specifications for Cyclone devices. The chapters contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Cyclone devices. This section contains the following chapters: Chapter 1. Introduction Chapter 2. Cyclone Architecture Chapter 3. Configuration & Testing Chapter 4. DC & Switching Characteristics Chapter 5. Reference & Ordering Information Revision History The table below shows the revision history for Chapters 1 through 5. Chapter(s) Date / Version Changes Made Added the EP1C4 device. Updated the "Timing Model" section. 1 through 5 May 2003 v1.0 Altera Corporation Section I-1 Preliminary Cyclone FPGA Family Data Sheet Cyclone Device Handbook, Volume 1 Section I-2 Preliminary Altera Corporation 1. Introduction C51001-1.0 Introduction The CycloneTM field programmable gate array family is based on a 1.5-V, 0.13-mm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz, 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new lowcost serial configuration devices to configure Cyclone devices. The following shows the main sections in the Cyclone FPGA Family Data Sheet: Section Page Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Embedded Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Global Clock Network & Phase-Locked Loops. . . . . . . . . . . 2-29 I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 Power Sequencing & Hot Socketing . . . . . . . . . . . . . . . . . . . . 2-55 IEEE Std. 1149.1 (JTAG) Boundary Scan Support . . . . . . . . . . 3-1 SignalTap II Embedded Logic Analyzer . . . . . . . . . . . . . . . . . 3-5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Altera Corporation May 2003 1-1 Preliminary Cyclone Device Handbook, Volume 1 Features The Cyclone device family offers the following features: 2,910 to 20,060 LEs, see Table 1-1 Up to 294,912 RAM bits (36,864 bytes) Supports configuration through low-cost serial configuration device Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards Support for 66-MHz, 32-bit PCI standard Low speed (311 Mbps) LVDS I/O support Up to two PLLs per device provide clock multiplication and phase shifting Up to eight global clock lines with six clock resources available per logic array block (LAB) row Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM Support for multiple intellectual property (IP) cores, including Altera MegaCore functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions. Table 1-1. Cyclone Device Features Feature LEs M4K RAM blocks (128 x 36 bits) Total RAM bits PLLs Maximum user I/O pins (1) Note to Table 1-1: (1) This parameter includes global clock pins. EP1C3 2,910 13 59,904 1 104 EP1C4 4,000 17 78,336 2 301 EP1C6 5,980 20 92,160 2 185 EP1C12 12,060 52 239,616 2 249 EP1C20 20,060 64 294,912 2 301 1-2 Preliminary Altera Corporation May 2003 Features Cyclone devices are available in quad flat pack (QFP) and space-saving FineLine BGA packages (see Table 1-2 through 1-3). Table 1-2. Cyclone Package Options & I/O Pin Counts Device EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 Notes to Table 1-2: (1) (2) TQFP: thin quad flat pack. PQFP: plastic quad flat pack. Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the EP1C3 device in the 144-pin TQFP package and the EP1C6 device in the same package) 100-Pin TQFP 144-Pin TQFP 240-Pin PQFP 256-Pin 324-Pin 400-Pin (1) (1), (2) (1) FineLine BGA FineLine BGA FineLine BGA 65 104 249 98 185 173 185 185 249 233 301 301 Table 1-3. Cyclone QFP & FineLine BGA Package Sizes Dimension Pitch (mm) Area (mm2) Length x width (mm x mm) 100-Pin TQFP 0.5 256 16 x 16 144-Pin TQFP 0.5 484 22 x 22 240-Pin PQFP 0.5 1,024 34.6 x 34.6 256-Pin FineLine BGA 1.0 289 17 x 17 324-Pin FineLine BGA 1.0 361 19 x 19 400-Pin FineLine BGA 1.0 441 21 x 21 Altera Corporation May 2003 1-3 Preliminary Cyclone Device Handbook, Volume 1 1-4 Preliminary Altera Corporation May 2003 2. Cyclone Architecture C51002-1.0 Functional Description Cyclone devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks. The logic array consists of LABs, with 10 LEs in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. Cyclone devices range between 2,910 to 20,060 LEs. M4K RAM blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 200 MHz. These blocks are grouped into columns across the device in between certain LABs. Cyclone devices offer between 60 to 288 Kbits of embedded RAM. Each Cyclone device I/O pin is fed by an I/O element (IOE) located at the ends of LAB rows and columns around the periphery of the device. I/O pins support various single-ended and differential I/O standards, such as the 66-MHz, 32-bit PCI standard and the LVDS I/O standard at up to 311 Mbps. Each IOE contains a bidirectional I/O buffer and three registers for registering input, output, and output-enable signals. Dualpurpose DQS, DQ, and DM pins along with delay chains (used to phasealign DDR signals) provide interface support with external memory devices such as DDR SDRAM, and FCRAM devices at up to 133 MHz (266 Mbps). Cyclone devices provide a global clock network and up to two PLLs. The global clock network consists of eight global clock lines that drive throughout the entire device. The global clock network can provide clocks for all resources within the device, such as IOEs, LEs, and memory blocks. The global clock lines can also be used for control signals. Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as external outputs for high-speed differential I/O support. Figure 2-1 shows a diagram of the Cyclone EP1C12 device. Altera Corporation May 2003 2-1 Preliminary Cyclone Device Handbook, Volume 1 Figure 2-1. Cyclone EP1C12 Device Block Diagram IOEs Logic Array PLL EP1C12 Device M4K Blocks The number of M4K RAM blocks, PLLs, rows, and columns vary per device. Table 2-1 lists the resources available in each Cyclone device. Table 2-1. Cyclone Device Resources M4K RAM Device Columns EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 1 1 1 2 2 PLLs Blocks 13 17 20 52 64 1 2 2 2 2 LAB Columns 24 26 32 48 64 LAB Rows 13 17 20 26 32 2-2 Preliminary Altera Corporation May 2003 Logic Array Blocks Logic Array Blocks Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect, look-up table (LUT) chain, and register chain connection lines. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the output of one LE's LUT to the adjacent LE for fast sequential LUT connections within the same LAB. Register chain connections transfer the output of one LE's register to the adjacent LE's register within an LAB. The Quartus II(R) Compiler places associated logic within an LAB or adjacent LABs, allowing the use of local, LUT chain, and register chain connections for performance and area efficiency. Figure 2-2 details the Cyclone LAB. Figure 2-2. Cyclone LAB Structure Row Interconnect Column Interconnect Direct link interconnect from adjacent block Direct link interconnect from adjacent block Direct link interconnect to adjacent block Direct link interconnect to adjacent block LAB Local Interconnect LAB Interconnects The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM blocks from the left and right can also drive an LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher Altera Corporation May 2003 2-3 Preliminary Cyclone Device Handbook, Volume 1 performance and flexibility. Each LE can drive 30 other LEs through fast local and direct link interconnects. Figure 2-3 shows the direct link connection. Figure 2-3. Direct Link Connection Direct link interconnect from left LAB, M4K memory block, PLL, or IOE output Direct link interconnect from right LAB, M4K memory block, PLL, or IOE output Direct link interconnect to left Direct link interconnect to right Local Interconnect LAB LAB Control Signals Each LAB contains dedicated logic for driving control signals to its LEs. The control signals include two clocks, two clock enables, two asynchronous clears, synchronous clear, asynchronous preset/load, synchronous load, and add/subtract control signals. This gives a maximum of 10 control signals at a time. Although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. Each LAB can use two clocks and two clock enable signals. Each LAB's clock and clock enable signals are linked. For example, any LE in a particular LAB using the labclk1 signal will also use labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses both LAB-wide clock signals. De-asserting the clock enable signal will turn off the LAB-wide clock. Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. The asynchronous load acts as a preset when the asynchronous load data input is tied high. 2-4 Preliminary Altera Corporation May 2003 Logic Elements With the LAB-wide addnsub control signal, a single LE can implement a one-bit adder and subtractor. This saves LE resources and improves performance for logic functions such as DSP correlators and signed multipliers that alternate between addition and subtraction depending on data. The LAB row clocks [5..0] and LAB local interconnect generate the LABwide control signals. The MultiTrackTM interconnect's inherent low skew allows clock and control signal distribution in addition to data. Figure 2-4 shows the LAB control signal generation circuit. Figure 2-4. LAB-Wide Control Signals Dedicated LAB Row Clocks Local Interconnect Local Interconnect 6 Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclk1 labclkena1 labclkena2 syncload labclr2 addnsub labclk2 asyncload or labpre labclr1 synclr Logic Elements The smallest unit of logic in the Cyclone architecture, the LE, is compact and provides advanced features with efficient logic utilization. Each LE contains a four-input LUT, which is a function generator that can implement any function of four variables. In addition, each LE contains a programmable register and carry chain with carry select capability. A single LE also supports dynamic single bit addition or subtraction mode selectable by an LAB-wide control signal. Each LE drives all types of interconnects: local, row, column, LUT chain, register chain, and direct link interconnects. See Figure 2-5. Altera Corporation May 2003 2-5 Preliminary Cyclone Device Handbook, Volume 1 Figure 2-5. Cyclone LE Register chain routing from previous LE LAB-wide Register Bypass Synchronous Load LAB-wide Packed Synchronous Register Select Clear LAB Carry-In addnsub Carry-In1 Carry-In0 Programmable Register LUT chain routing to next LE Row, column, and direct link routing data1 data2 data3 data4 ENA CLRN Look-Up Table (LUT) Carry Chain Synchronous Load and Clear Logic PRN/ALD D Q ADATA Row, column, and direct link routing labclr1 labclr2 labpre/aload Chip-Wide Reset Asynchronous Clear/Preset/ Load Logic Local Routing Clock & Clock Enable Select labclk1 labclk2 labclkena1 labclkena2 Register Feedback Register chain output Carry-Out0 Carry-Out1 LAB Carry-Out Each LE's programmable register can be configured for D, T, JK, or SR operation. Each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any internal logic can drive the register's clock and clear control signals. Either general-purpose I/O pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous data. The asynchronous load data input comes from the data3 input of the LE. For combinatorial functions, the LUT output bypasses the register and drives directly to the LE outputs. Each LE has three outputs that drive the local, row, and column routing resources. The LUT or register output can drive these three outputs independently. Two LE outputs drive column or row and direct link routing connections and one drives local interconnect resources. This allows the LUT to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and the LUT for unrelated 2-6 Preliminary Altera Corporation May 2003 Logic Elements functions. Another special packing mode allows the register output to feed back into the LUT of the same LE so that the register is packed with its own fan-out LUT. This provides another mechanism for improved fitting. The LE can also drive out registered and unregistered versions of the LUT output. LUT Chain & Register Chain In addition to the three general routing outputs, the LEs within an LAB have LUT chain and register chain outputs. LUT chain connections allow LUTs within the same LAB to cascade together for wide input functions. Register chain outputs allow registers within the same LAB to cascade together. The register chain output allows an LAB to use LUTs for a single combinatorial function and the registers to be used for an unrelated shift register implementation. These resources speed up connections between LABs while saving local interconnect resources. "MultiTrack Interconnect" on page 2-12 for more information on LUT chain and register chain connections. addnsub Signal The LE's dynamic adder/subtractor feature saves logic resources by using one set of LEs to implement both an adder and a subtractor. This feature is controlled by the LAB-wide control signal addnsub. The addnsub signal sets the LAB to perform either A + B or A - B. The LUT computes addition; subtraction is computed by adding the two's complement of the intended subtractor. The LAB-wide signal converts to two's complement by inverting the B bits within the LAB and setting carry-in = 1 to add one to the least significant bit (LSB). The LSB of an adder/subtractor must be placed in the first LE of the LAB, where the LAB-wide addnsub signal automatically sets the carry-in to 1. The Quartus II(R) Compiler automatically places and uses the adder/subtractor feature when using adder/subtractor parameterized functions. LE Operating Modes The Cyclone LE can operate in one of the following modes: Normal mode Dynamic arithmetic mode Each mode uses LE resources differently. In each mode, eight available inputs to the LEthe four data inputs from the LAB local interconnect, carry-in0 and carry-in1 from the previous LE, the LAB carry-in from the previous carry-chain LAB, and the register chain connectionare directed to different destinations to implement the Altera Corporation May 2003 2-7 Preliminary Cyclone Device Handbook, Volume 1 desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset/load, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all LE modes. The addnsub control signal is allowed in arithmetic mode. The Quartus II(R) software, in conjunction with parameterized functions such as library of parameterized modules (LPM) functions, automatically chooses the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. If required, the designer can also create special-purpose functions that specify which LE operating mode to use for optimal performance. Normal Mode The normal mode is suitable for general logic applications and combinatorial functions. In normal mode, four data inputs from the LAB local interconnect are inputs to a four-input LUT (see Figure 2-6). The Quartus II(R) Compiler automatically selects the carry-in or the data3 signal as one of the inputs to the LUT. Each LE can use LUT chain connections to drive its combinatorial output directly to the next LE in the LAB. Asynchronous load data for the register comes from the data3 input of the LE. LEs in normal mode support packed registers. Figure 2-6. LE in Normal Mode sload sclear (LAB Wide) (LAB Wide) Register chain connection aload (LAB Wide) addnsub (LAB Wide) (1) data1 data2 data3 cin (from cout of previous LE) data4 4-Input LUT ALD/PRE ADATA Q D ENA CLRN Row, column, and direct link routing Row, column, and direct link routing clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide) Local routing LUT chain connection Register chain output Register Feedback Note to Figure 2-6: (1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain. 2-8 Preliminary Altera Corporation May 2003 Logic Elements Dynamic Arithmetic Mode The dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. An LE in dynamic arithmetic mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first two 2-input LUTs compute two summations based on a possible carry-in of 1 or 0; the other two LUTs generate carry outputs for the two chains of the carry select circuitry. As shown in Figure 2-7, the LAB carry-in signal selects either the carry-in0 or carry-in1 chain. The selected chain's logic level in turn determines which parallel sum is generated as a combinatorial or registered output. For example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 + data2 + carry-in0 or data1 + data2 + carry-in1 The other two LUTs use the data1 and data2 signals to generate two possible carry-out signalsone for a carry of 1 and the other for a carry of 0. The carry-in0 signal acts as the carry select for the carry-out0 output and carry-in1 acts as the carry select for the carry-out1 output. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. The dynamic arithmetic mode also offers clock enable, counter enable, synchronous up/down control, synchronous clear, synchronous load, and dynamic adder/subtractor options. The LAB local interconnect data inputs generate the counter enable and synchronous up/down control signals. The synchronous clear and synchronous load options are LABwide signals that affect all registers in the LAB. The Quartus II(R) software automatically places any registers that are not used by the counter into other LABs. The addnsub LAB-wide signal controls whether the LE acts as an adder or subtractor. Altera Corporation May 2003 2-9 Preliminary Cyclone Device Handbook, Volume 1 Figure 2-7. LE in Dynamic Arithmetic Mode LAB Carry-In Carry-In0 Carry-In1 addnsub (LAB Wide) (1) sload sclear (LAB Wide) (LAB Wide) Register chain connection aload (LAB Wide) data1 data2 data3 LUT ALD/PRE ADATA Q D ENA CLRN Row, column, and direct link routing Row, column, and direct link routing LUT LUT clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide) Local routing LUT LUT chain connection Register chain output Register Feedback Carry-Out0 Carry-Out1 Note to Figure 2-7: (1) The addnsub signal is tied to the carry input for the first LE of a carry chain only. Carry-Select Chain The carry-select chain provides a very fast carry-select function between LEs in dynamic arithmetic mode. The carry-select chain uses the redundant carry calculation to increase the speed of carry functions. The LE is configured to calculate outputs for a possible carry-in of 0 and carryin of 1 in parallel. The carry-in0 and carry-in1 signals from a lowerorder bit feed forward into the higher-order bit via the parallel carry chain and feed into both the LUT and the next portion of the carry chain. Carry-select chains can begin in any LE within an LAB. The speed advantage of the carry-select chain is in the parallel precomputation of carry chains. Since the LAB carry-in selects the precomputed carry chain, not every LE is in the critical path. Only the propagation delays between LAB carry-in generation (LE 5 and LE 10) are now part of the critical path. This feature allows the Cyclone architecture to implement high-speed counters, adders, multipliers, parity functions, and comparators of arbitrary width. 2-10 Preliminary Altera Corporation May 2003 Logic Elements Figure 2-8 shows the carry-select circuitry in an LAB for a 10-bit full adder. One portion of the LUT generates the sum of two bits using the input signals and the appropriate carry-in bit; the sum is routed to the output of the LE. The register can be bypassed for simple adders or used for accumulator functions. Another portion of the LUT generates carryout bits. An LAB-wide carry-in bit selects which chain is used for the addition of given inputs. The carry-in signal for each chain, carry-in0 or carry-in1, selects the carry-out to carry forward to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it is fed to local, row, or column interconnects. Figure 2-8. Carry Select Chain LAB Carry-In A1 B1 A2 B2 0 LE1 1 Sum1 LAB Carry-In Carry-In0 Carry-In1 LE2 Sum2 LUT data1 data2 Sum LUT A3 B3 A4 B4 LE3 Sum3 LE4 Sum4 LUT A5 B5 LE5 Sum5 LUT 0 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 LE6 1 Sum6 Carry-Out0 Carry-Out1 LE7 Sum7 LE8 Sum8 LE9 Sum9 LE10 Sum10 LAB Carry-Out Altera Corporation May 2003 2-11 Preliminary Cyclone Device Handbook, Volume 1 The Quartus II(R) Compiler automatically creates carry chain logic during design processing, or the designer can create it manually during design entry. Parameterized functions such as LPM functions automatically take advantage of carry chains for the appropriate functions. The Quartus II(R) Compiler creates carry chains longer than 10 LEs by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically allowing fast horizontal connections to M4K memory blocks. A carry chain can continue as far as a full column. Clear & Preset Logic Control LAB-wide signals control the logic for the register's clear and preset signals. The LE directly supports an asynchronous clear and preset function. The register preset is achieved through the asynchronous load of a logic high. The direct asynchronous preset does not require a NOTgate push-back technique. Cyclone devices support simultaneous preset/ asynchronous load and clear signals. An asynchronous clear signal takes precedence if both signals are asserted simultaneously. Each LAB supports up to two clears and one preset signal. In addition to the clear and preset ports, Cyclone devices provide a chipwide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II(R) software controls this pin. This chip-wide reset overrides all other control signals. MultiTrack Interconnect In the Cyclone architecture, connections between LEs, M4K memory blocks, and device I/O pins are provided by the MultiTrack interconnect structure with DirectDriveTM technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different speeds used for inter- and intra-design block connectivity. The Quartus II(R) Compiler automatically places critical design paths on faster interconnects to improve design performance. DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement within the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycles that typically follow design changes and additions. The MultiTrack interconnect consists of row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when 2-12 Preliminary Altera Corporation May 2003 MultiTrack Interconnect migrating through different device densities. Dedicated row interconnects route signals to and from LABs, PLLs, and M4K memory blocks within the same row. These row resources include: Direct link interconnects between LABs and adjacent blocks R4 interconnects traversing four blocks to the right or left The direct link interconnect allows an LAB or M4K memory block to drive into the local interconnect of its left and right neighbors. Only one side of a PLL block interfaces with direct link and row interconnects. The direct link interconnect provides fast communication between adjacent LABs and/or blocks without using row interconnect resources. The R4 interconnects span four LABs, or two LABs and one M4K RAM block. These resources are used for fast row connections in a four-LAB region. Every LAB has its own set of R4 interconnects to drive either left or right. Figure 2-9 shows R4 interconnect connections from an LAB. R4 interconnects can drive and be driven by M4K memory blocks, PLLs, and row IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4 interconnect. For R4 interconnects that drive to the right, the primary LAB and right neighbor can drive on to the interconnect. For R4 interconnects that drive to the left, the primary LAB and its left neighbor can drive on to the interconnect. R4 interconnects can drive other R4 interconnects to extend the range of LABs they can drive. R4 interconnects can also drive C4 interconnects for connections from one row to another. Altera Corporation May 2003 2-13 Preliminary Cyclone Device Handbook, Volume 1 Figure 2-9. R4 Interconnect Connections Adjacent LAB can Drive onto Another LAB's R4 Interconnect R4 Interconnect Driving Left C4 Column Interconnects (1) R4 Interconnect Driving Right LAB Neighbor Primary LAB (2) LAB Neighbor Notes to Figure 2-9: (1) (2) C4 interconnects can drive R4 interconnects. This pattern is repeated for every LAB in the LAB row. The column interconnect operates similarly to the row interconnect. Each column of LABs is served by a dedicated column interconnect, which vertically routes signals to and from LABs, M4K memory blocks, and row and column IOEs. These column resources include: LUT chain interconnects within an LAB Register chain interconnects within an LAB C4 interconnects traversing a distance of four blocks in an up and down direction Cyclone devices include an enhanced interconnect structure within LABs for routing LE output to LE input connections faster using LUT chain connections and register chain connections. The LUT chain connection allows the combinatorial output of an LE to directly drive the fast input of the LE right below it, bypassing the local interconnect. These resources can be used as a high-speed connection for wide fan-in functions from LE 1 to LE 10 in the same LAB. The register chain connection allows the register output of one LE to connect directly to the register input of the next LE in the LAB for fast shift registers. The Quartus II(R) Compiler automatically takes advantage of these resources to improve utilization and performance. Figure 2-10 shows the LUT chain and register chain interconnects. 2-14 Preliminary Altera Corporation May 2003 MultiTrack Interconnect Figure 2-10. LUT Chain & Register Chain Interconnects Local Interconnect Routing Among LEs in the LAB LUT Chain Routing to Adjacent LE LE 1 LE 2 Register Chain Routing to Adjacent LE's Register Input Local Interconnect LE 3 LE 4 LE 5 LE 6 LE 7 LE 8 LE 9 LE 10 The C4 interconnects span four LABs or M4K blocks up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. Figure 2-11 shows the C4 interconnect connections from an LAB in a column. The C4 interconnects can drive and be driven by all types of architecture blocks, including PLLs, M4K memory blocks, and column and row IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. Altera Corporation May 2003 2-15 Preliminary Cyclone Device Handbook, Volume 1 Figure 2-11. C4 Interconnect Connections Note (1) C4 Interconnect Drives Local and R4 Interconnects Up to Four Rows C4 Interconnect Driving Up LAB Row Interconnect Adjacent LAB can drive onto neighboring LAB's C4 interconnect Local Interconnect C4 Interconnect Driving Down Note to Figure 2-11: (1) Each C4 interconnect can drive either up or down four rows. 2-16 Preliminary Altera Corporation May 2003 MultiTrack Interconnect All embedded blocks communicate with the logic array similar to LABto-LAB interfaces. Each block (i.e., M4K memory or PLL) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. Table 2-2 shows the Cyclone device's routing scheme. Table 2-2. Cyclone Device Routing Scheme Destination Direct Link Interconnect Local Interconnect Register Chain Source LUT Chain M4K RAM Block R4 Interconnect C4 Interconnect Column IOE v LUT Chain Register Chain Local Interconnect Direct Link Interconnect R4 Interconnect C4 Interconnect LE M4K RAM Block PLL Column IOE Row IOE v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v Altera Corporation May 2003 2-17 Preliminary Row IOE PLL LE Cyclone Device Handbook, Volume 1 Embedded Memory The Cyclone embedded memory consists of columns of M4K memory blocks. EP1C3 and EP1C6 devices have one column of M4K blocks, while EP1C12 and EP1C20 devices have two columns (see Table 1-1 on page 1-2 for total RAM bits per density). Each M4K block can implement various types of memory with or without parity, including true dualport, simple dual-port, and single-port RAM, ROM, and FIFO buffers. The M4K blocks support the following features: 4,608 RAM bits 200 MHz performance True dual-port memory Simple dual-port memory Single-port memory Byte enable Parity bits Shift register FIFO buffer ROM Mixed clock mode Memory Modes The M4K memory blocks include input registers that synchronize writes and output registers to pipeline designs and improve system performance. M4K blocks offer a true dual-port mode to support any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. Figure 2-12 shows true dual-port memory. Figure 2-12. True Dual-Port Memory Configuration A dataA[ ] addressA[ ] wrenA clockA clockenA qA[ ] aclrA B dataB[ ] addressB[ ] wrenB clockB clockenB qB[ ] aclrB In addition to true dual-port memory, the M4K memory blocks support simple dual-port and single-port RAM. Simple dual-port memory supports a simultaneous read and write. Single-port memory supports non-simultaneous reads and writes. Figure 2-13 shows these different M4K RAM memory port configurations. 2-18 Preliminary Altera Corporation May 2003 Embedded Memory Figure 2-13. Simple Dual-Port & Single-Port Memory Configurations Simple Dual-Port Memory data[ ] wraddress[ ] wren inclock inclocken inaclr rdaddress[ ] rden q[ ] outclock outclocken outaclr Single-Port Memory (1) data[ ] address[ ] wren inclock inclocken inaclr q[ ] outclock outclocken outaclr Note to Figure 2-13: (1) Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size. The memory blocks also enable mixed-width data ports for reading and writing to the RAM ports in dual-port RAM configuration. For example, the memory block can be written in x1 mode at port A and read out in x16 mode from port B. The Cyclone memory architecture can implement fully synchronous RAM by registering both the input and output signals to the M4K RAM block. All M4K memory block inputs are registered, providing synchronous write cycles. In synchronous operation, the memory block generates its own self-timed strobe write enable (wren) signal derived from a global clock. In contrast, a circuit using asynchronous RAM must generate the RAM wren signal while ensuring its data and address signals meet setup and hold time specifications relative to the wren signal. The output registers can be bypassed. Pseudo-asynchronous reading is possible in the simple dual-port mode of M4K blocks by clocking the read enable and read address registers on the negative clock edge and bypassing the output registers. Altera Corporation May 2003 2-19 Preliminary Cyclone Device Handbook, Volume 1 When configured as RAM or ROM, the designer can use an initialization file to pre-load the memory contents. Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size. The Quartus II(R) software automatically implements larger memory by combining multiple M4K memory blocks. For example, two 256x16-bit RAM blocks can be combined to form a 256x32-bit RAM block. Memory performance does not degrade for memory blocks using the maximum number of words allowed. Logical memory blocks using less than the maximum number of words use physical blocks in parallel, eliminating any external control logic that would increase delays. To create a larger high-speed memory block, the Quartus II(R) software automatically combines memory blocks with LE control logic. Parity Bit Support The M4K blocks support a parity bit for each byte. The parity bit, along with internal LE logic, can implement parity checking for error detection to ensure data integrity. Designers can also use parity-size data words to store user-specified control bits. Byte enables are also available for data input masking during write operations. Shift Register Support The designer can configure M4K memory blocks to implement shift registers for DSP applications such as pseudo-random number generators, multi-channel filtering, auto-correlation, and crosscorrelation functions. These and other DSP applications require local data storage, traditionally implemented with standard flip-flops, which can quickly consume many logic cells and routing resources for large shift registers. A more efficient alternative is to use embedded memory as a shift register block, which saves logic cell and routing resources and provides a more efficient implementation with the dedicated circuitry. The size of a w x m x n shift register is determined by the input data width (w), the length of the taps (m), and the number of taps (n). The size of a w x m x n shift register must be less than or equal to the maximum number of memory bits in the M4K block (4,608 bits). The total number of shift register outputs (number of taps n x width w) must be less than the maximum data width of the M4K RAM block (x36). To create larger shift registers, multiple memory blocks are cascaded together. 2-20 Preliminary Altera Corporation May 2003 Embedded Memory Data is written into each address location at the falling edge of the clock and read from the address at the rising edge of the clock. The shift register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. Figure 2-14 shows the M4K memory block in the shift register mode. Figure 2-14. Shift Register Memory Configuration w x m x n Shift Register m-Bit Shift Register w w m-Bit Shift Register w w n Number of Taps m-Bit Shift Register w w m-Bit Shift Register w w Memory Configuration Sizes The memory address depths and output widths can be configured as 4,096 x 1, 2,048 x 2, 1,024 x 4, 512 x 8 (or 512 x 9 bits), 256 x 16 (or 256 x 18 bits), and 128 x 32 (or 128 x 36 bits). The 128 x 32- or 36-bit configuration Altera Corporation May 2003 2-21 Preliminary Cyclone Device Handbook, Volume 1 is not available in the true dual-port mode. Mixed-width configurations are also possible, allowing different read and write widths. Tables 2-3 and 2-4 summarize the possible M4K RAM block configurations. Table 2-3. M4K RAM Block Configurations (Simple Dual-Port) Write Port Read Port 4K x 1 4K x 1 2K x 2 1K x 4 512 x 8 256 x 16 128 x 32 512 x 9 256 x 18 128 x 36 2K x 2 v v v v v v 1K x 4 v v v v v v 512 x 8 v v v v v v 256 x 16 v v v v v v 128 x 32 v v v v v v 512 x 9 256 x 18 128 x 36 v v v v v v v v v v v v v v v Table 2-4. M4K RAM Block Configurations (True Dual-Port) Port B Port A 4K x 1 4K x 1 2K x 2 1K x 4 512 x 8 256 x 16 512 x 9 256 x 18 2K x 2 v v v v v 1K x 4 v v v v v 512 x 8 v v v v v 256 x 16 v v v v v 512 x 9 256 x 18 v v v v v v v v v When the M4K RAM block is configured as a shift register block, the designer can create a shift register up to 4,608 bits (w x m x n). 2-22 Preliminary Altera Corporation May 2003 Embedded Memory Byte Enables M4K blocks support byte writes when the write port has a data width of 16, 18, 32, or 36 bits. The byte enables allow the input data to be masked so the device can write to specific bytes. The unwritten bytes retain the previous written value. Table 2-5 summarizes the byte selection. Table 2-5. Byte Enable for M4K Blocks byteena[3..0] [0] = 1 [1] = 1 [2] = 1 [3] = 1 Notes to Table 2-5: (1) (2) Notes (1), (2) datain x 36 [8..0] [17..9] [26..18] [35..27] datain x 18 [8..0] [17..9] - - Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, i.e., in x16 and x32 modes. Control Signals & M4K Interface The M4K blocks allow for different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M4K block registers (renwe, address, byte enable, datain, and output registers). Only the output register can be bypassed. The six labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K block. LEs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure 2-15. The R4, C4, and direct link interconnects from adjacent LABs drive the M4K block local interconnect. The M4K blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 10 direct link input connections to the M4K block are possible from the left adjacent LABs and another 10 possible from the right adjacent LAB. M4K block outputs can also connect to left and right LABs through 10 direct link interconnects each. Figure 2-16 shows the M4K block to logic array interface. Altera Corporation May 2003 2-23 Preliminary Cyclone Device Handbook, Volume 1 Figure 2-15. M4K RAM Block Control Signals Dedicated LAB Row Clocks Local Interconnect 6 Local Interconnect Local Interconnect Local Interconnect Local Interconnect clocken_a Local Interconnect clock_a renwe_a alcr_b clocken_b alcr_a renwe_b clock_b Local Interconnect Local Interconnect Local Interconnect Local Interconnect Figure 2-16. M4K RAM Block LAB Row Interface C4 Interconnects R4 Interconnects Direct link interconnect to adjacent LAB 10 Direct link interconnect to adjacent LAB dataout Direct link interconnect from adjacent LAB M4K RAM Block Byte enable Control Signals Clocks Direct link interconnect from adjacent LAB address datain 6 M4K RAM Block Local Interconnect Region LAB Row Clocks 2-24 Preliminary Altera Corporation May 2003 Embedded Memory Independent Clock Mode The M4K memory blocks implement independent clock mode for true dual-port memory. In this mode, a separate clock is available for each port (ports A and B). Clock A controls all registers on the port A side, while clock B controls all registers on the port B side. Each port, A and B, also supports independent clock enables and asynchronous clear signals for port A and B registers. Figure 2-17 shows an M4K memory block in independent clock mode. Figure 2-17. Independent Clock Mode 6 LAB Row Clocks Note (1) A 6 dataA[ ] D ENA Q Data In Memory Block 256 16 (2) 512 8 1,024 4 2,048 2 4,096 1 B 6 Data In Q D ENA dataB[ ] byteenaA[ ] D ENA Q Byte Enable A Byte Enable B Q D ENA byteenaB[ ] addressA[ ] D ENA Q Address A Address B Q D ENA addressB[ ] wrenA wrenB Write/Read Enable clkenA clockA D ENA Q Write Pulse Generator Write/Read Enable Write Pulse Generator Q D ENA clkenB clockB Data Out Data Out D ENA Q Q D ENA qA [ ] qB [ ] Note to Figure 2-17: (1) All registers shown have asynchronous clear ports. Input/Output Clock Mode Input/output clock mode can be implemented for both the true and simple dual-port memory modes. On each of the two ports, A or B, one clock controls all registers for inputs into the memory block: data input, wren, and address. The other clock controls the block's data output registers. Each memory block port, A or B, also supports independent clock enables and asynchronous clear signals for input and output registers. Figures 2-18 and 2-19 show the memory block in input/output clock mode. Altera Corporation May 2003 2-25 Preliminary Cyclone Device Handbook, Volume 1 Figure 2-18. Input/Output Clock Mode in True Dual-Port Mode 6 LAB Row Clocks 6 dataA[ ] D ENA Q Note (1) A Data In Memory Block 256 x 16 (2) 512 x 8 1,024 x 4 2,048 x 2 4,096 x 1 B Data In Q D ENA 6 dataB[ ] byteenaA[ ] D ENA Q Byte Enable A Byte Enable B Q D ENA byteenaB[ ] addressA[ ] D ENA Q Address A Address B Q D ENA addressB[ ] wrenA wrenB clkenA clockA D ENA Q Write Pulse Generator Write/Read Enable Write/Read Enable Write Pulse Generator Q D ENA Data Out Data Out clkenB D ENA Q Q D ENA clockB qA[ ] qB[ ] Note to Figure 2-18: (1) All registers shown have asynchronous clear ports. 2-26 Preliminary Altera Corporation May 2003 Embedded Memory Figure 2-19. Input/Output Clock Mode in Simple Dual-Port Mode 6 LAB Row Clocks 6 data[ ] D Q ENA Note (1) Memory Block 256 16 Data In 512 8 1,024 4 2,048 2 4,096 1 Read Address address[ ] D Q ENA Data Out byteena[ ] D Q ENA Byte Enable D Q ENA To MultiTrack Interconnect wraddress[ ] D Q ENA Write Address rden D Q ENA wren Read Enable outclken inclken inclock D Q ENA Write Pulse Generator Write Enable outclock Note to Figure 2-19: (1) All registers shown except the rden register have asynchronous clear ports. Read/Write Clock Mode The M4K memory blocks implement read/write clock mode for simple dual-port memory. The designer can use up to two clocks in this mode. The write clock controls the block's data inputs, wraddress, and wren. The read clock controls the data output, rdaddress, and rden. The memory blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. Figure 2-20 shows a memory block in read/write clock mode. Altera Corporation May 2003 2-27 Preliminary Cyclone Device Handbook, Volume 1 Figure 2-20. Read/Write Clock Mode in Simple Dual-Port Mode 6 LAB Row Clocks 6 data[ ] D Q ENA Note (1) Memory Block 256 x 16 512 x 8 1,024 x 4 Data In 2,048 x 2 4,096 x 1 Data Out D Q ENA To MultiTrack Interconnect address[ ] D Q ENA Read Address wraddress[ ] D Q ENA Write Address byteena[ ] D Q ENA Byte Enable rden D Q ENA wren Read Enable rdclken wrclken wrclock D Q ENA Write Pulse Generator Write Enable rdclock Note to Figure 2-20: (1) All registers shown except the rden register have asynchronous clear ports. Single-Port Mode The M4K memory blocks also support single-port mode, used when simultaneous reads and writes are not required. See Figure 2-21. A single M4K memory block can support up to two single-port mode RAM blocks if each RAM block is less than or equal to 2K bits in size. 2-28 Preliminary Altera Corporation May 2003 Global Clock Network & Phase-Locked Loops Figure 2-21. Single-Port Mode 6 LAB Row Clocks 6 data[ ] D Q ENA RAM/ROM 256 x 16 512 x 8 1,024 x 4 Data In 2,048 x 2 4,096 x 1 Data Out D Q ENA To MultiTrack Interconnect address[ ] D Q ENA Address wren Write Enable outclken inclken inclock D Q ENA Write Pulse Generator outclock Global Clock Network & Phase-Locked Loops Cyclone devices provide a global clock network and up to two PLLs for a complete clock management solution. Global Clock Network There are four dedicated clock pins (CLK[3..0], two pins on the left side and two pins on the right side) that drive the global clock network, as shown in Figure 2-22. PLL outputs, logic array, and dual-purpose clock (DPCLK[7..0]) pins can also drive the global clock network. The eight global clock lines in the global clock network drive throughout the entire device. The global clock network can provide clocks for all resources within the device IOEs, LEs, and memory blocks. The global clock lines can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin, or DQS signals for DDR SDRAM or FCRAM interfaces. Internal logic can also drive the global clock network for internally generated global clocks and Altera Corporation May 2003 2-29 Preliminary Cyclone Device Handbook, Volume 1 asynchronous clears, clock enables, or other control signals with large fanout. Figure 2-22 shows the various sources that drive the global clock network. Figure 2-22. Global Clock Generation Note (1) DPCLK3 DPCLK2 Cyclone Device Global Clock Network 8 DPCLK1 From logic array 4 From logic array 4 DPCLK4 CLK0 CLK1 (3) PLL1 2 4 4 2 PLL2 (2) CLK2 CLK3 (3) DPCLK0 DPCLK5 DPCLK7 DPCLK6 Notes to Figure 2-22: (1) (2) (3) The EP1C3 device in the 100-pin TQFP package has five DPCLK pins (DPCLK2, DPCLK3, DPCLK4, DPCLK6, and DPCLK7). EP1C3 devices only contain one PLL (PLL 1). The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins CLK1 and CLK3. Dual-Purpose Clock Pins Each Cyclone device except the EP1C3 device has eight dual-purpose clock pins, DPCLK[7..0] (two on each I/O bank). EP1C3 devices have five DPCLK pins in the 100-pin TQFP package. These dual-purpose pins 2-30 Preliminary Altera Corporation May 2003 Global Clock Network & Phase-Locked Loops can connect to the global clock network (see Figure 2-22) for high-fanout control signals such as clocks, asynchronous clears, presets, and clock enables, or protocol control signals such as TRDY and IRDY for PCI, or DQS signals for external memory interfaces. Combined Resources Each Cyclone device contains eight distinct dedicated clocking resources. The device uses multiplexers with these clocks to form six-bit buses to drive LAB row clocks, column IOE clocks, or row IOE clocks. See Figure 2-23. Another multiplexer at the LAB level selects two of the six LAB row clocks to feed the LE registers within the LAB. Figure 2-23. Global Clock Network Multiplexers Column I/O Region IO_CLK]5..0] Global Clock Network Global Clocks [3..0] Dual-Purpose Clocks [7..0] PLL Outputs [3..0] Core Logic [7..0] Clock [7..0] LAB Row Clock [5..0] Row I/O Region IO_CLK[5..0] IOE clocks have row and column block regions. Six of the eight global clock resources feed to these row and column regions. Figure 2-24 shows the I/O clock regions. Altera Corporation May 2003 2-31 Preliminary Cyclone Device Handbook, Volume 1 Figure 2-24. I/O Clock Regions Column I/O Clock Region IO_CLK[5..0] 6 I/O Clock Regions Cyclone Logic Array LAB Row Clocks labclk[5..0] 6 LAB Row Clocks labclk[5..0] 6 8 LAB Row Clocks labclk[5..0] 6 LAB Row Clocks labclk[5..0] Global Clock Network 6 Row I/O Regions LAB Row Clocks labclk[5..0] 6 LAB Row Clocks labclk[5..0] 6 I/O Clock Regions 6 Column I/O Clock Region IO_CLK[5..0] PLLs Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as outputs for differential I/O support. Cyclone devices contain two PLLs, except for the EP1C3 device, which contains one PLL. 2-32 Preliminary Altera Corporation May 2003 Global Clock Network & Phase-Locked Loops Table 2-6 shows the PLL features in Cyclone devices. Figure 2-25 shows a Cyclone PLL. Table 2-6. Cyclone PLL Features Feature Clock multiplication and division Phase shift Programmable duty cycle Number of internal clock outputs Number of external clock outputs Notes to Table 2-6: (1) (2) (3) The m counter ranges from 2 to 32. The n counter and the post-scale counters range from 1 to 32. The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by 8. For degree increments, Cyclone devices can shift all output frequencies in increments of 45. Smaller degree increments are possible depending on the frequency and divide parameters. The EP1C3 device in the 100-pin TQFP package does not support external clock output. The EP1C6 device in the 144-pin TQFP package does not support external clock output from PLL2. PLL Support m/(n x post-scale counter) (1) Down to 156-ps increments (2), (3) Yes 2 One differential or one single-ended (4) (4) Figure 2-25. Cyclone PLL Note (1) VCO Phase Selection Selectable at Each PLL Output Port Post-Scale Counters CLK0 or LVDSCLK1p (2) /n CLK1 or LVDSCLK1n (2) t /m /g0 Charge Pump Loop Filter Global clock t PFD (3) VCO /g1 Global clock /e I/O buffer Notes to Figure 2-25: (1) (2) The EP1C3 device in the 100-pin TQFP package does not support external outputs or LVDS inputs. The EP1C6 device in the 144-pin TQFP package does not support external output from PLL2. LVDS input is supported via the secondary function of the dedicated clock pins. For PLL 1, the CLK0 pin's secondary function is LVDSCLK1p and the CLK1 pin's secondary function is LVDSCLK1n. For PLL 2, the CLK2 pin's secondary function is LVDSCLK2p and the CLK3 pin's secondary function is LVDSCLK2n. PFD: phase frequency detector. (3) Altera Corporation May 2003 2-33 Preliminary Cyclone Device Handbook, Volume 1 Figure 2-26 shows the PLL global clock connections. Figure 2-26. Cyclone PLL Global Clock Connections G1 G0 G2 G3 G4 G5 G6 G7 g0 CLK0 CLK1 (1) PLL1 g1 e PLL1_OUT (3), (4) g0 g1 PLL2 e PLL2_OUT (3), (4) CLK2 CLK3 (2) Notes to Figure 2-26: (1) (2) (3) (4) PLL 1 supports one single-ended or LVDS input via pins CLK0 and CLK1. PLL2 supports one single-ended or LVDS input via pins CLK2 and CLK3. PLL1_OUT and PLL2_OUT support single-ended or LVDS output. If external output is not required, these pins are available as regular user I/O pins. The EP1C3 device in the 100-pin TQFP package does not support external clock output. The EP1C6 device in the 144-pin TQFP package does not support external clock output from PLL2. Table 2-7 shows the global clock network sources available in Cyclone devices. Table 2-7. Global Clock Network Sources (Part 1 of 2) Source PLL Counter Output PLL1 G0 PLL1 G1 PLL2 G0 (1) PLL2 G1 (1) Dedicated Clock Input Pins CLK0 CLK1 (2) CLK2 CLK3 (2) GCLK0 GCLK1 v GCLK2 v GCLK3 GCLK4 GCLK5 GCLK6 GCLK7 v v v v v v v v v v v v v v 2-34 Preliminary Altera Corporation May 2003 Global Clock Network & Phase-Locked Loops Table 2-7. Global Clock Network Sources (Part 2 of 2) Source Dual-Purpose Clock Pins DPCLK0 (3) DPCLK1 (3) DPCLK2 DPCLK3 DPCLK4 DPCLK5 (3) DPCLK6 DPCLK7 Notes to Table 2-7: (1) (2) (3) EP1C3 devices only have one PLL (PLL 1). EP1C3 devices in the 100-pin TQFP package do not have dedicated clock pins CLK1 and CLK3. EP1C3 devices in the 100-pin TQFP package do not have the DPCLK0, DPCLK1, or DPCLK5 pins. GCLK0 GCLK1 GCLK2 GCLK3 v GCLK4 GCLK5 GCLK6 GCLK7 v v v v v v v Clock Multiplication & Division Cyclone PLLs provide clock synthesis for PLL output ports using m/(n x post scale counter) scaling factors. The input clock is divided by a prescale divider, n, and is then multiplied by the m feedback factor. The control loop drives the VCO to match fIN x (m/n). Each output port has a unique post-scale counter to divide down the high-frequency VCO. For multiple PLL outputs with different frequencies, the VCO is set to the least-common multiple of the output frequencies that meets its frequency specifications. Then, the post-scale dividers scale down the output frequency for each output port. For example, if the output frequencies required from one PLL are 33 and 66 MHz, the VCO is set to 330 MHz (the least-common multiple in the VCO's range). Each PLL has one pre-scale divider, n, that can range in value from 1 to 32. Each PLL also has one multiply divider, m, that can range in value from 2 to 32. Global clock outputs have two post scale G dividers for global clock outputs, and external clock outputs have an E divider for external clock output, both ranging from 1 to 32. The Quartus II(R) software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered. Altera Corporation May 2003 2-35 Preliminary Cyclone Device Handbook, Volume 1 External Clock Inputs Each PLL supports single-ended or differential inputs for sourcesynchronous receivers or for general-purpose use. The dedicated clock pins (CLK[3..0]) feed the PLL inputs. These dual-purpose pins can also act as LVDS input pins. See Figure 2-25. Table 2-8 shows the I/O standards supported by PLL input and output pins. Table 2-8. PLL I/O Standards I/O Standard 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI LVDS SSTL-2 class I SSTL-2 class II SSTL-3 class I SSTL-3 class II Differential SSTL-2 CLK Input v v v v v v v v v v EXTCLK Output v v v v v v v v v v v For more information on LVDS I/O support, see "LVDS I/O Pins" on page 2-54. External Clock Outputs Each PLL supports one differential or one single-ended output for source-synchronous transmitters or for general-purpose external clocks. If the PLL does not use these PLL_OUT pins, the pins are available for use as general-purpose I/O pins. The PLL_OUT pins support all I/O standards shown in Table 2-8. The external clock outputs do not have their own VCC and ground voltage supplies. Therefore, to minimize jitter, do not place switching I/O pins next to these output pins. The EP1C3 device in the 100-pin TQFP package 2-36 Preliminary Altera Corporation May 2003 Global Clock Network & Phase-Locked Loops does not have dedicated clock output pins. The EP1C6 device in the 144-pin TQFP package only supports dedicated clock outputs from PLL 1. Clock Feedback Cyclone PLLs have three modes for multiplication and/or phase shifting: Zero delay buffer modeThe external clock output pin is phasealigned with the clock input pin for zero delay. Normal modeIf the design uses an internal PLL clock output, the normal mode compensates for the internal clock delay from the input clock pin to the IOE registers. The external clock output pin is phase shifted with respect to the clock input pin if connected in this mode. The designer defines which internal clock output from the PLL should be phase-aligned to compensate for internal clock delay. No compensation modeIn this mode, the PLL will not compensate for any clock networks. Phase Shifting Cyclone PLLs have an advanced clock shift capability that enables programmable phase shifts. Designers can enter a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. Designers can perform phase shifting in time units with a resolution range of 156 to 417 ps. The finest resolution equals one eighth of the VCO period. The VCO period is a function of the frequency input and the multiplication and division factors. Each clock output counter can choose a different phase of the VCO period from up to eight taps. Designers can use this clock output counter along with an initial setting on the post-scale counter to achieve a phase-shift range for the entire period of the output clock. The phase tap feedback to the m counter can shift all outputs to a single phase. The Quartus II(R) software automatically sets the phase taps and counter settings according to the phase shift entered. Lock Detect Signal The lock output indicates that there is a stable clock output signal in phase with the reference clock. Without any additional circuitry, the lock signal may toggle as the PLL begins tracking the reference clock. Therefore, the designer may need to gate the lock signal for use as a system-control signal. Altera Corporation May 2003 2-37 Preliminary Cyclone Device Handbook, Volume 1 Programmable Duty Cycle The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature is supported on each PLL post-scale counter (g0, g1, e). The duty cycle setting is achieved by a low- and hightime count setting for the post-scale dividers. The Quartus II(R) software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. Control Signals There are three control signals for clearing and enabling PLLs and their outputs. The designer can use these signals to control PLL resynchronization and the ability to gate PLL output clocks for lowpower applications. The pllenable signal enables and disables PLLs. When the pllenable signal is low, the clock output ports are driven by ground and all the PLLs go out of lock. When the pllenable signal goes high again, the PLLs relock and resynchronize to the input clocks. An input pin or LE output can drive the pllenable signal. The areset signals are reset/resynchronization inputs for each PLL. Cyclone devices can drive these input signals from input pins or from LEs. When areset is driven high, the PLL counters will reset, clearing the PLL output and placing the PLL out of lock. When driven low again, the PLL will resynchronize to its input as it relocks. The pfdena signals control the phase frequency detector (PFD) output with a programmable gate. If you disable the PFD, the VCO will operate at its last set value of control voltage and frequency with some drift, and the system will continue running when the PLL goes out of lock or the input clock disables. By maintaining the last locked frequency, the system has time to store its current settings before shutting down. The designer can either use their own control signal or gated locked status signals to trigger the pfdena signal. f For more information on Cyclone PLLs, see Chapter 6, Using PLLs in Cyclone Devices. 2-38 Preliminary Altera Corporation May 2003 I/O Structure I/O Structure IOEs support many features, including: Differential and single-ended I/O standards 3.3-V, 32-bit, 66-MHz PCI compliance Joint Test Action Group (JTAG) boundary-scan test (BST) support Output drive strength control Weak pull-up resistors during configuration Slew-rate control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors in user mode Programmable input and output delays Open-drain outputs DQ and DQS I/O pins Cyclone device IOEs contain a bidirectional I/O buffer and three registers for complete embedded bidirectional single data rate transfer. Figure 2-27 shows the Cyclone IOE structure. The IOE contains one input register, one output register, and one output enable register. The designer can use the input registers for fast setup times and output registers for fast clock-to-output times. Additionally, the designer can use the output enable (OE) register for fast clock-to-output enable timing. The Quartus(R)II software automatically duplicates a single OE register that controls multiple output or bidirectional pins. IOEs can be used as input, output, or bidirectional pins. Altera Corporation May 2003 2-39 Preliminary Cyclone Device Handbook, Volume 1 Figure 2-27. Cyclone IOE Structure Logic Array OE Register OE D Q Output Register Output D Q Combinatorial input (1) Input Input Register D Q Note to Figure 2-27: (1) There are two paths available for combinatorial inputs to the logic array. Each path contains a unique programmable delay chain. The IOEs are located in I/O blocks around the periphery of the Cyclone device. There are up to three IOEs per row I/O block and up to three IOEs per column I/O block (column I/O blocks span two columns). The row I/O blocks drive row, column, or direct link interconnects. The column I/O blocks drive column interconnects. Figure 2-28 shows how a row I/O block connects to the logic array. Figure 2-29 shows how a column I/O block connects to the logic array. 2-40 Preliminary Altera Corporation May 2003 I/O Structure Figure 2-28. Row I/O Block Connection to the Interconnect R4 Interconnects C4 Interconnects I/O Block Local Interconnect 21 Data and Control Signals from Logic Array (1) LAB 21 Row I/O Block io_datain[2..0] and comb_io_datain[2..0] (2) Direct Link Interconnect to Adjacent LAB LAB Local Interconnect Direct Link Interconnect from Adjacent LAB io_clk[5:0] Row I/O Block Contains up to Three IOEs Notes to Figure 2-28: (1) The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output enables, io_coe[2..0], three input clock enables, io_cce_in[2..0], three output clock enables, io_cce_out[2..0], three clocks, io_cclk[2..0], three asynchronous clear signals, io_caclr[2..0], and three synchronous clear signals, io_csclr[2..0]. Each of the three IOEs in the row I/O block can have one io_datain input (combinatorial or registered) and one comb_io_datain (combinatorial) input. (2) Altera Corporation May 2003 2-41 Preliminary Cyclone Device Handbook, Volume 1 Figure 2-29. Column I/O Block Connection to the Interconnect Column I/O Block Contains up to Three IOEs Column I/O Block 21 Data & Control Signals from Logic Array (1) 21 IO_datain[2:0] & comb_io_datain[2..0] (2) io_clk[5..0] I/O Block Local Interconnect R4 Interconnects LAB LAB LAB LAB Local Interconnect C4 Interconnects Notes to Figure 2-29: (1) The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output enables, io_coe[2..0], three input clock enables, io_cce_in[2..0], three output clock enables, io_cce_out[2..0], three clocks, io_cclk[2..0], three asynchronous clear signals, io_caclr[2..0], and three synchronous clear signals, io_csclr[2..0]. Each of the three IOEs in the column I/O block can have one io_datain input (combinatorial or registered) and one comb_io_datain (combinatorial) input. (2) 2-42 Preliminary Altera Corporation May 2003 I/O Structure The pin's datain signals can drive the logic array. The logic array drives the control and data signals, providing a flexible routing resource. The row or column IOE clocks, io_clk[5..0], provide a dedicated routing resource for low-skew, high-speed clocks. The global clock network generates the IOE clocks that feed the row or column I/O regions (see "Global Clock Network & Phase-Locked Loops" on page 2-29). Figure 2-30 illustrates the signal paths through the I/O block. Figure 2-30. Signal Path through the I/O Block Row or Column io_clk[5..0] To Other IOEs To Logic Array io_datain comb_io_datain oe ce_in io_csclr ce_out io_coe io_cce_in Data and Control Signal Selection aclr/preset sclr clk_in io_caclr clk_out io_cclk io_dataout dataout IOE From Logic Array io_cce_out Each IOE contains its own control signal selection for the following control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset, clk_in, and clk_out. Figure 2-31 illustrates the control signal selection. Altera Corporation May 2003 2-43 Preliminary Cyclone Device Handbook, Volume 1 Figure 2-31. Control Signal Selection per IOE Dedicated I/O Clock [5..0] Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect io_coe io_csclr io_caclr io_cce_out io_cce_in clk_out ce_out sclr/preset io_cclk clk_in ce_in aclr/preset oe In normal bidirectional operation, the designer can use the input register for input data requiring fast setup times. The input register can have its own clock input and clock enable separate from the OE and output registers. The output register can be used for data requiring fast clock-tooutput performance. The OE register is available for fast clock-to-output enable timing. The OE and output register share the same clock source and the same clock enable source from the local interconnect in the associated LAB, dedicated I/O clocks, or the column and row interconnects. Figure 2-32 shows the IOE in bidirectional configuration. 2-44 Preliminary Altera Corporation May 2003 I/O Structure Figure 2-32. Cyclone IOE in Bidirectional I/O Configuration ioe_clk[5..0] Column or Row Interconect OE OE Register D PRN Q VCCIO clkout ENA CLRN Optional PCI Clamp VCCIO ce_out aclr/prn Programmable Pull-Up Resistor Chip-Wide Reset Output Register PRN D Q Output Pin Delay ENA sclr/preset CLRN Drive Strength Control Open-Drain Output Slew Control Input Pin to Logic Array Delay comb_datain data_in Bus Hold Input Pin to Input Register Delay or Input Pin to Logic Array Delay Input Register PRN D Q clkin ce_in ENA CLRN The Cyclone device IOE includes programmable delays to ensure zero hold times, minimize setup times, or increase clock to output times. A path in which a pin directly drives a register may require a programmable delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. Programmable delays decrease input-pin-to-logic-array and IOE input register delays. The Quartus II(R) Compiler can program these delays to automatically minimize setup time while providing a zero hold Altera Corporation May 2003 2-45 Preliminary Cyclone Device Handbook, Volume 1 time. Programmable delays can increase the register-to-pin delays for output registers. Table 2-9 shows the programmable delays for Cyclone devices. Table 2-9. Cyclone Programmable Delay Chain Programmable Delays Input pin to logic array delay Input pin to input register delay Output pin delay Quartus II(R) Logic Option Decrease input delay to internal cells Decrease input delay to input registers Increase delay to output pin There are two paths in the IOE for a combinatorial input to reach the logic array. Each of the two paths can have a different delay. This allows the designer to adjust delays from the pin to internal LE registers that reside in two different areas of the device. The designer sets the two combinatorial input delays by selecting different delays for two different paths under the Decrease input delay to internal cells logic option in the Quartus II(R) software. When the input signal requires two different delays for the combinatorial input, the input register in the IOE is no longer available. The IOE registers in Cyclone devices share the same source for clear or preset. The designer can program preset or clear for each individual IOE. The designer can also program the registers to power up high or low after configuration is complete. If programmed to power up low, an asynchronous clear can control the registers. If programmed to power up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of another device's active-low input upon power up. If one register in an IOE uses a preset or clear signal then all registers in the IOE must use that same signal if they require preset or clear. Additionally a synchronous reset signal is available to the designer for the IOE registers. External RAM Interfacing Cyclone devices support DDR SDRAM and FCRAM interfaces at up to 133 MHz through dedicated circuitry. DDR SDRAM & FCRAM Cyclone devices have dedicated circuitry for interfacing with DDR SDRAM. All I/O banks support DDR SDRAM and FCRAM I/O pins. However, the configuration input pins in bank 1 must operate at 2.5 V because the SSTL-2 VCCIO level is 2.5 V. Additionally, the configuration 2-46 Preliminary Altera Corporation May 2003 I/O Structure output pins (nSTATUS and CONF_DONE) and all the JTAG pins in I/O bank 3 must operate at 2.5 V because the VCCIO level of SSTL-2 is 2.5 V. I/O banks 1, 2, 3, and 4 support DQS signals with DQ bus modes of x 8. For x 8 mode, there are up to eight groups of programmable DQS and DQ pins, I/O banks 1, 2, 3, and 4 each have two groups in the 324-pin and 400-pin FineLine BGA packages. Each group consists of one DQS pin, a set of eight DQ pins, and one DM pin (see Figure 2-33). Each DQS pin drives the set of eight DQ pins within that group. Figure 2-33. Cyclone Device DQ & DQS Groups in x 8 Mode Top, Bottom, Left, or Right I/O Bank Note (1) DQ Pins DQS Pin DM Pin Note to Figure 2-33: (1) Each DQ group consists of one DQS pin, eight DQ pins, and one DM pin. Table 2-10 shows the number of DQ pin groups per device. Table 2-10. DQ Pin Groups (Part 1 of 2) Device EP1C3 Package 100-pin TQFP (1) 144-pin TQFP Number of x 8 DQ Pin Groups 3 4 8 8 Total DQ Pin Count 24 32 64 64 EP1C4 324-pin FineLine BGA 400-pin FineLine BGA Altera Corporation May 2003 2-47 Preliminary Cyclone Device Handbook, Volume 1 Table 2-10. DQ Pin Groups (Part 2 of 2) Device EP1C6 Package 144-pin TQFP 240-pin PQFP 256-pin FineLine BGA Number of x 8 DQ Pin Groups 4 4 4 4 4 8 8 8 Total DQ Pin Count 32 32 32 32 32 64 64 64 EP1C12 240-pin PQFP 256-pin FineLine BGA 324-pin FineLine BGA EP1C20 324-pin FineLine BGA 400-pin FineLine BGA Note to Table 2-10: (1) EP1C3 devices in the 100-pin TQFP package do not have any DQ pin groups in I/O bank 1. A programmable delay chain on each DQS pin allows for either a 90 phase shift (for DDR SDRAM), or a 72 phase shift (for FCRAM) which automatically center-aligns input DQS synchronization signals within the data window of their corresponding DQ data signals. The phaseshifted DQS signals drive the global clock network. This global DQS signal clocks DQ signals on internal LE registers. These DQS delay elements combine with the PLL's clocking and phase shift ability to provide a complete hardware solution for interfacing to high-speed memory. The clock phase shift allows the PLL to clock the DQ output enable and output paths. The designer should use the following guidelines to meet 133 MHz performance for DDR SDRAM and FCRAM interfaces: The DQS signal must be in the middle of the DQ group it clocks Resynchronize the incoming data to the logic array clock using successive LE registers or FIFO buffers LE registers must be placed in the LAB adjacent to the DQ I/O pin column it is fed by Figure 2-34 illustrates DDR SDRAM and FCRAM interfacing from the I/O through the dedicated circuitry to the logic array. 2-48 Preliminary Altera Corporation May 2003 I/O Structure Figure 2-34. DDR SDRAM & FCRAM Interfacing DQS OE OE LE Register DQ OE OE LE Register Output LE Register VCC t clk Output LE Register GND OE LE Register Output LE Registers OE LE Register DataA Input LE Registers -90 clk Output LE Registers DataB Input LE Registers Adjacent LAB LEs PLL Programmable Delay Chain Global Clock Phase Shifted -90 LE Register LE Register Adjacent LAB LEs Resynchronizing Global Clock Programmable Drive Strength The output buffer for each Cyclone device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL and LVCMOS standards have several levels of drive strength that the designer can control. SSTL-3 class I and II, and SSTL-2 class I and II support a minimum setting, the lowest drive strength that guarantees the IOH/IOL of the standard. Using minimum settings provides signal slew Altera Corporation May 2003 2-49 Preliminary Cyclone Device Handbook, Volume 1 rate control to reduce system noise and signal overshoot. Table 2-11 shows the possible settings for the I/O standards with drive strength control. Table 2-11. Programmable Drive Strength I/O Standard LVTTL (3.3 V) IOH/IOL Current Strength Setting (mA) 4 8 12 16 24 LVCMOS (3.3 V) 2 4 8 12 LVTTL (2.5 V) 2 8 12 16 LVTTL (1.8 V) 2 8 12 LVCMOS (1.5 V) 2 4 8 Open-Drain Output Cyclone devices provide an optional open-drain (equivalent to an opencollector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and writeenable signals) that can be asserted by any of several devices. Slew-Rate Control The output buffer for each Cyclone device I/O pin has a programmable output slew-rate control that can be configured for low noise or highspeed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces 2-50 Preliminary Altera Corporation May 2003 I/O Structure system noise, but adds a nominal delay to rising and falling edges. Each I/O pin has an individual slew-rate control, allowing the designer to specify the slew rate on a pin-by-pin basis. The slew-rate control affects both the rising and falling edges. Bus Hold Each Cyclone device I/O pin provides an optional bus-hold feature. The bus-hold circuitry can hold the signal on an I/O pin at its last-driven state. Since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not necessary to hold a signal level when the bus is tri-stated. The bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. The designer can select this feature individually for each I/O pin. The bus-hold output will drive no higher than VCCIO to prevent overdriving signals. If the bus-hold feature is enabled, the device cannot use the programmable pull-up option. Disable the bus-hold feature when the I/O pin is configured for differential signals. The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately 7 k to pull the signal level to the last-driven state. Table 4-15 on page 4-6 gives the specific sustaining current for each VCCIO voltage level driven through this resistor and overdrive current used to identify the next-driven input level. The bus-hold circuitry is only active after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. Programmable Pull-Up Resistor Each Cyclone device I/O pin provides an optional programmable pullup resistor during user mode. If the designer enables this feature for an I/O pin, the pull-up resistor (typically 25 k) holds the output to the VCCIO level of the output pin's bank. Altera Corporation May 2003 2-51 Preliminary Cyclone Device Handbook, Volume 1 Advanced I/O Standard Support Cyclone device IOEs support the following I/O standards: 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI LVDS SSTL-2 class I and II SSTL-3 class I and II Differential SSTL-2 class II (on output clocks only) Table 2-12 describes the I/O standards supported by Cyclone devices. Table 2-12. Cyclone I/O Standards I/O Standard 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI (1) LVDS (2) SSTL-2 class I and II SSTL-3 class I and II Differential SSTL-2 (3) Notes to Table 2-12: (1) (2) (3) EP1C3 devices do not support PCI. EP1C3 devices in the 100-pin TQFP package do not support the LVDS I/O standard. This I/O standard is only available on output clock pins (PLL_OUT pins). Type Single-ended Single-ended Single-ended Single-ended Single-ended Differential Voltage-referenced Voltage-referenced Differential Output Supply Input Reference Voltage (VREF) (V) Voltage (VCCIO) (V) N/A N/A N/A N/A N/A N/A 1.25 1.5 1.25 3.3 2.5 1.8 1.5 3.3 2.5 2.5 3.3 2.5 Board Termination Voltage (VTT) (V) N/A N/A N/A N/A N/A N/A 1.25 1.5 1.25 Cyclone devices contain four I/O banks, as shown in Figure 2-35. I/O banks 1 and 3 support all the I/O standards listed in Table 2-12. I/O banks 2 and 4 support all the I/O standards listed in Table 2-12 except the 3.3-V PCI standard. I/O banks 2 and 4 contain dual-purpose DQS, DQ, and DM pins to support a DDR SDRAM or FCRAM interface. I/O bank 1 can also support a DDR SDRAM or FCRAM interface, however, the configuration input pins in I/O bank 1 must operate at 2.5 V. I/O bank 3 can also support a DDR SDRAM or FCRAM interface, however, all the JTAG pins in I/O bank 3 must operate at 2.5 V. 2-52 Preliminary Altera Corporation May 2003 I/O Structure Figure 2-35. Cyclone I/O Banks Notes (1), (2) I/O Bank 2 I/O Bank 1 Also Supports the 3.3-V PCI I/O Standard I/O Bank 1 All I/O Banks Support 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS LVDS SSTL-2 Class I and II SSTL-3 Class I and II I/O Bank 3 Also Supports the 3.3-V PCI I/O Standard I/O Bank 3 Individual Power Bus I/O Bank 4 Notes to Figure 2-35: (1) (2) Figure 2-35 is a top view of the silicon die. Figure 2-35 is a graphic representation only. Refer to the pin list and the Quartus II(R) software for exact pin locations. Each I/O bank has its own VCCIO pins. A single device can support 1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces; each individual bank can support a different standard with different I/O voltages. Each bank also has dualpurpose VREF pins to support any one of the voltage-referenced standards (e.g., SSTL-3) independently. If an I/O bank does not use voltage-referenced standards, the VREF pins are available as user I/O pins. Each I/O bank can support multiple standards with the same VCCIO for input and output pins. For example, when VCCIO is 3.3-V, a bank can support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs. Altera Corporation May 2003 2-53 Preliminary Cyclone Device Handbook, Volume 1 LVDS I/O Pins A subset of pins in all four I/O banks supports LVDS interfacing. These dual-purpose LVDS pins require an external-resistor network at the transmitter channels in addition to 100- termination resistors on receiver channels. These pins do not contain dedicated serialization or deserialization circuitry; therefore, internal logic performs serialization and deserialization functions. Table 2-13 shows the total number of supported LVDS channels per device density. Table 2-13. Cyclone Device LVDS Channels Device EP1C3 Pin Count 100 144 Number of LVDS Channels (1) 34 103 129 29 72 72 66 72 103 95 129 EP1C4 324 400 EP1C6 144 240 256 EP1C12 240 256 324 EP1C20 324 400 Note to Table 2-13: (1) EP1C3 devices in the 100-pin TQFP package do not support the LVDS I/O standard. MultiVolt I/O Interface The Cyclone architecture supports the MultiVolt I/O interface feature, which allows Cyclone devices in all packages to interface with systems of different supply voltages. The devices have one set of VCC pins for internal operation and input buffers (VCCINT), and four sets for I/O output drivers (VCCIO). The Cyclone VCCINT pins must always be connected to a 1.5-V power supply. If the VCCINT level is 1.5 V, then input pins are 1.5-V, 1.8-V, 2.5-V, and 3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-V, 2-54 Preliminary Altera Corporation May 2003 Power Sequencing & Hot Socketing 1.8-V, 2.5-V, or 3.3-V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as the power supply (i.e., when VCCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems). When VCCIO pins are connected to a 3.3-V power supply, the output high is 3.3-V and is compatible with 3.3-V or 5.0-V systems. Table 2-14 summarizes Cyclone MultiVolt I/O support. Table 2-14. Cyclone MultiVolt I/O Support VCCIO (V) 1.5 1.8 2.5 3.3 Notes to Table 2-14: (1) (2) (3) (4) (5) (6) (7) (8) Note (1) Output Signal 3.3 V v (2) Input Signal 1.5 V v 1.8 V v v 2.5 V v (2) 5.0 V 1.5 V v v (3) v (5) 1.8 V 2.5 V 3.3 V 5.0 V v v v (4) v v v v (6) v v (5) v v (7) v v (8) v (7) v (7) The PCI clamping diode must be disabled to drive an input with voltages higher than VCCIO. When VCCIO = 1.5-V and a 2.5-V or 3.3-V input signal feeds an input pin, higher pin leakage current is expected. When VCCIO = 1.8-V, a Cyclone device can drive a 1.5-V device with 1.8-V tolerant inputs. When VCCIO = 3.3-V and a 2.5-V input signal feeds an input pin, the VCCIO supply current will be slightly larger than expected. When VCCIO = 2.5-V, a Cyclone device can drive a 1.5-V or 1.8-V device with 2.5-V tolerant inputs. Cyclone devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode. When VCCIO = 3.3-V, a Cyclone device can drive a 1.5-V, 1.8-V, or 2.5-V device with 3.3-V tolerant inputs. When VCCIO = 3.3-V, a Cyclone device can drive a device with 5.0-V LVTTL inputs but not 5.0-V LVCMOS inputs. Power Sequencing & Hot Socketing Because Cyclone devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. Therefore, the VCCIO and VCCINT power supplies may be powered in any order. Signals can be driven into Cyclone devices before and during power up without damaging the device. In addition, Cyclone devices do not drive out during power up. Once operating conditions are reached and the device is configured, Cyclone devices operate as specified by the user. Altera Corporation May 2003 2-55 Preliminary Cyclone Device Handbook, Volume 1 2-56 Preliminary Altera Corporation May 2003 3. Configuration & Testing C51003-1.0 IEEE Std. 1149.1 (JTAG) Boundary Scan Support All Cyclone devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be performed either before or after, but not during configuration. Cyclone devices can also use the JTAG port for configuration together with either the Quartus II(R) software or hardware using either Jam Files (.jam) or Jam Byte-Code Files (.jbc). Cyclone devices support reconfiguring the I/O standard settings on the IOE through the JTAG BST chain. The JTAG chain can update the I/O standard for all input and output pins any time before or during user mode. Designers can use this ability for JTAG testing before configuration when some of the Cyclone pins drive or receive from other devices on the board using voltage-referenced standards. Since the Cyclone device might not be configured before JTAG testing, the I/O pins might not be configured for appropriate electrical standards for chip-to-chip communication. Programming those I/O standards via JTAG allows designers to fully test I/O connection to other devices. The JTAG pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O standards. The TDO pin voltage is determined by the VCCIO of the bank where it resides. The bank VCCIO selects whether the JTAG inputs are 1.5-V, 1.8-V, 2.5-V, or 3.3-V compatible. Cyclone devices also use the JTAG port to monitor the operation of the device with the SignalTap II embedded logic analyzer. Cyclone devices support the JTAG instructions shown in Table 3-1. Table 3-1. Cyclone JTAG Instructions (Part 1 of 2) JTAG Instruction SAMPLE/PRELOAD Instruction Code 00 0000 0101 Description Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. Also used by the SignalTap II embedded logic analyzer. Allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation. EXTEST (1) 00 0000 0000 BYPASS 11 1111 1111 Altera Corporation May 2003 3-1 Preliminary Cyclone Device Handbook, Volume 1 Table 3-1. Cyclone JTAG Instructions (Part 2 of 2) JTAG Instruction USERCODE Instruction Code 00 0000 0111 Description Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding I/O pins to a state defined by the data in the boundary-scan register. Used when configuring a Cyclone device via the JTAG port with a MasterBlasterTM or ByteBlasterMVTM download cable, or when using a Jam File or Jam Byte-Code File via an embedded processor. IDCODE HIGHZ (1) 00 0000 0110 00 0000 1011 CLAMP (1) 00 0000 1010 ICR instructions PULSE_NCONFIG CONFIG_IO 00 0000 0001 00 0000 1101 Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected. Allows configuration of I/O standards through the JTAG chain for JTAG testing. Can be executed before, after, or during configuration. Stops configuration if executed during configuration. Once issued, the CONFIG_IO instruction will hold nSTATUS low to reset the configuration device. nSTATUS is held low until the device is reconfigured. Monitors internal device operation with the SignalTap II embedded logic analyzer. SignalTap II instructions Note to Table 3-1: (1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST. 3-2 Preliminary Altera Corporation May 2003 IEEE Std. 1149.1 (JTAG) Boundary Scan Support The Cyclone device instruction register length is 10 bits and the USERCODE register length is 32 bits. Tables 3-2 and 3-3 show the boundary-scan register length and device IDCODE information for Cyclone devices. Table 3-2. Cyclone Boundary-Scan Register Length Device EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 Boundary-Scan Register Length 339 930 582 774 930 Table 3-3. 32-Bit Cyclone Device IDCODE IDCODE (32 bits) (1) Device Version (4 Bits) EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 (1) (2) Part Number (16 Bits) 0010 0000 1000 0001 0010 0000 1000 0101 0010 0000 1000 0010 0010 0000 1000 0011 0010 0000 1000 0100 Manufacturer Identity (11 Bits) 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 LSB (1 Bit) (2) 1 1 1 1 1 0000 0000 0000 0000 0000 Notes to Table 3-3: The most significant bit (MSB) is on the left. The IDCODE's least significant bit (LSB) is always 1. Altera Corporation May 2003 3-3 Preliminary Cyclone Device Handbook, Volume 1 Figure 3-1 shows the timing requirements for the JTAG signals. Figure 3-1. Cyclone JTAG Waveforms TMS TDI t JCP t JCH TCK tJPZX TDO tJSSU Signal to Be Captured Signal to Be Driven tJSH t JPCO t JPXZ t JCL t JPSU t JPH tJSZX tJSCO tJSXZ Table 3-4 shows the JTAG timing parameters and values for Cyclone devices. Table 3-4. Cyclone JTAG Timing Parameters & Values Symbol tJ C P tJ C H tJ C L tJ P S U tJ P H tJ P C O tJ P Z X tJ P X Z tJ S S U tJ S H tJ S C O tJ S Z X tJ S X Z Parameter TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance Min 100 50 50 20 45 Max Unit ns ns ns ns ns 25 25 25 20 45 35 35 35 ns ns ns ns ns ns ns ns 3-4 Preliminary Altera Corporation May 2003 SignalTap II Embedded Logic Analyzer f For more information on JTAG, see the following documents: Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) Jam Programming & Test Language Specification SignalTap II Embedded Logic Analyzer Cyclone devices feature the SignalTap II embedded logic analyzer, which monitors design operation over a period of time through the IEEE Std. 1149.1 (JTAG) circuitry. A designer can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is particularly important for advanced packages, such as FineLine BGA packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured. The logic, circuitry, and interconnects in the Cyclone architecture are configured with CMOS SRAM elements. Cyclone devices are reconfigurable and are 100% tested prior to shipment. As a result, the designer does not have to generate test vectors for fault coverage purposes, and can instead focus on simulation and design verification. In addition, the designer does not need to manage inventories of different ASIC designs. Cyclone devices can be configured on the board for the specific functionality required. Cyclone devices are configured at system power-up with data stored in an Altera configuration device or provided by a system controller. The Cyclone device's optimized interface allows the device to act as controller in an active serial configuration scheme with the new low-cost serial configuration device. Cyclone devices can be configured in under 120 ms using serial data at 20 MHz. The serial configuration device can be programmed via the ByteBlaster II download cable, the Altera Programming Unit (APU), or third-party programmers. In addition to the new low-cost serial configuration device, Altera offers in-system programmability (ISP)-capable configuration devices that can configure Cyclone devices via a serial data stream. The interface also enables microprocessors to treat Cyclone devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy. After a Cyclone device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Real-time changes can be made during system operation, enabling innovative reconfigurable computing applications. Configuration Altera Corporation May 2003 3-5 Preliminary Cyclone Device Handbook, Volume 1 Operating Modes The Cyclone architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called configuration. During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. Together, the configuration and initialization processes are called command mode. Normal device operation is called user mode. SRAM configuration elements allow Cyclone devices to be reconfigured in-circuit by loading new configuration data into the device. With realtime reconfiguration, the device is forced into command mode with a device pin. The configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. Designers can perform in-field upgrades by distributing new configuration files either within the system or remotely. A built-in weak pull-up resistor pulls all user I/O pins to VCCIO before and during device configuration. The configuration pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O standards. The voltage level of the configuration output pins is determined by the VCCIO of the bank where the pins reside. The bank VCCIO selects whether the configuration inputs are 1.5-V, 1.8-V, 2.5-V, or 3.3-V compatible. Configuration Schemes Designers can load the configuration data for a Cyclone device with one of three configuration schemes (see Table 3-5), chosen on the basis of the target application. Designers can use a configuration device, intelligent controller, or the JTAG port to configure a Cyclone device. A low-cost configuration device can automatically configure a Cyclone device at system power-up. 3-6 Preliminary Altera Corporation May 2003 Configuration Multiple Cyclone devices can be configured in any of the three configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device. Table 3-5. Data Sources for Configuration Configuration Scheme Active serial Passive serial (PS) Data Source Low-cost serial configuration device Enhanced or EPC2 configuration device, MasterBlaster or ByteBlasterMV download cable, or serial data source MasterBlaster or ByteBlasterMV download cable or a microprocessor with a Jam or JBC file JTAG Altera Corporation May 2003 3-7 Preliminary Cyclone Device Handbook, Volume 1 3-8 Preliminary Altera Corporation May 2003 4. DC & Switching Characteristics C51004-1.0 Operating Conditions Cyclone devices are offered in both commercial and industrial grades. However, industrial-grade devices may have limited speed-grade availability. Tables 4-1 through 4-16 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for Cyclone devices. Table 4-1. Cyclone Device Absolute Maximum Ratings Symbol VCCINT VCCIO VI IOUT TSTG TAMB TJ DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature No bias Under bias Notes (1), (2) Minimum -0.5 -0.5 -0.5 -25 -65 -65 Parameter Supply voltage Conditions With respect to ground (3) Maximum 2.4 4.6 4.6 25 150 135 135 Unit V V V mA C C C BGA packages under bias Table 4-2. Cyclone Device Recommended Operating Conditions (Part 1 of 2) Symbol VCCINT VCCIO Parameter Supply voltage for internal logic and input buffers Supply voltage for output buffers, 3.3-V operation Supply voltage for output buffers, 2.5-V operation Supply voltage for output buffers, 1.8-V operation Supply voltage for output buffers, 1.5-V operation Conditions (4) (4) (4) (4) (4) (3), (5) Minimum 1.425 3.00 2.375 1.71 1.4 -0.5 Maximum 1.575 3.60 2.625 1.89 1.6 4.1 Unit V V V V V V VI Input voltage Altera Corporation May 2003 4-1 Preliminary Cyclone Device Handbook, Volume 1 Table 4-2. Cyclone Device Recommended Operating Conditions (Part 2 of 2) Symbol VO TJ Parameter Output voltage Operating junction temperature Conditions Minimum 0 Maximum VCCIO 85 100 40 40 Unit V C C ns ns For commercial use For industrial use 0 -40 tR tF Input rise time Input fall time Table 4-3. Cyclone Device DC Operating Conditions Symbol II IOZ ICC0 Note (6) Minimum -10 -10 10 Parameter Input pin leakage current Tri-stated I/O pin leakage current VCC supply current (standby) (All M4K blocks in powerdown mode) Conditions VI = VC C I O m a x to 0 V (7) VO = VC C I O m a x to 0 V (7) VI = ground, no load, no toggling inputs Typical Maximum 10 10 Unit A A mA RCONF Value of I/O pin pull- VCCIO = 3.0 V (8) up resistor before VCCIO = 2.375 V (8) and during configuration VCCIO = 1.71 V (8) 20 30 60 50 80 150 k k k Table 4-4. LVTTL Specifications Symbol VCCIO VI H VIL VOH VOL Parameter Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 3.0 1.7 -0.5 Maximum 3.6 4.1 0.7 Unit V V V V IOH = -4 to -24 mA (9) IOL = 4 to 24 mA (9) 2.4 0.45 V 4-2 Preliminary Altera Corporation May 2003 Operating Conditions Table 4-5. LVCMOS Specifications Symbol VCCIO VIH VIL VOH VOL Parameter Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 3.0 1.7 -0.5 Maximum 3.6 4.1 0.7 Unit V V V V VCCIO = 3.0, IOH = -0.1 mA VCCIO = 3.0, IOL = 0.1 mA VCCIO - 0.2 0.2 V Table 4-6. 2.5-V I/O Specifications Symbol VCCIO VIH VIL VOH Note (9) Conditions Minimum 2.375 1.7 -0.5 IOH = -0.1 mA IOH = -1 mA IOH = -2 to -16 mA (9) 2.1 2.0 1.7 0.2 0.4 0.7 Parameter Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Maximum 2.625 4.1 0.7 Unit V V V V V V V V V VOL Low-level output voltage IOL = 0.1 mA IOH = 1 mA IOH = 2 to 16 mA (9) Table 4-7. 1.8-V I/O Specifications Symbol VCCIO VI H VIL VOH VOL Parameter Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 1.65 0.65 x VCCIO -0.3 Maximum 1.95 2.25 0.35 x VCCIO Unit V V V V IOH = -2 to -8 mA (9) IOL = 2 to 8 mA (9) VCCIO - 0.45 0.45 V Altera Corporation May 2003 4-3 Preliminary Cyclone Device Handbook, Volume 1 Table 4-8. 1.5-V I/O Specifications Symbol VCCIO VI H VIL VOH VOL Parameter Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 1.4 0.65 x VCCIO -0.3 0.75 x VCCIO Maximum 1.6 VCCIO + 0.3 0.35 x VCCIO 0.25 x VCCIO Unit V V V V V IOH = -2 mA (9) IOL = 2 mA (9) Table 4-9. 2.5-V LVDS I/O Specifications Symbol VCCIO VOD VOD VOS VOS VTH VIN RL Note (10) Conditions Minimum 2.375 Parameter I/O supply voltage Differential output voltage Change in VOD between high and low Output offset voltage Change in VOS between high and low Differential input threshold Receiver input voltage range Receiver differential input resistor Typical 2.5 Maximum 2.625 550 50 Unit V mV mV V mV mV V W RL = 100 RL = 100 RL = 100 RL = 100 VCM = 1.2 V 250 1.125 1.25 1.375 50 -100 0.0 90 100 100 2.4 110 Table 4-10. 3.3-V PCI Specifications Symbol VCCIO VIH VIL VOH VOL Parameter Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 3.0 0.5 x VCCIO -0.5 Typical 3.3 Maximum 3.6 VCCIO + 0.5 0.3 x VCCIO Unit V V V V IOUT = -500 A IOUT = 1,500 A 0.9 x VCCIO 0.1 x VCCIO V 4-4 Preliminary Altera Corporation May 2003 Operating Conditions Table 4-11. SSTL-2 Class I Specifications Symbol VCCIO VTT VREF VIH VIL VOH VOL Parameter Output supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 2.375 VR E F - 0.04 1.15 VR E F + 0.18 -0.3 Typical 2.5 VR E F 1.25 Maximum 2.625 VR E F + 0.04 1.35 3.0 VR E F - 0.18 Unit V V V V V V IOH = -8.1 mA (9) IOL = 8.1 mA (9) VTT + 0.57 VT T - 0.57 V Table 4-12. SSTL-2 Class II Specifications Symbol VCCIO VTT VREF VIH VIL VOH VOL Parameter Output supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 2.3 VR E F - 0.04 1.15 VR E F + 0.18 -0.3 Typical 2.5 VR E F 1.25 Maximum 2.7 VR E F + 0.04 1.35 VCCIO + 0.3 VR E F - 0.18 Unit V V V V V V IOH = -16.4 mA (9) IOL = 16.4 mA (9) VTT + 0.76 VT T - 0.76 V Table 4-13. SSTL-3 Class I Specifications Symbol VCCIO VTT VREF VIH VIL VOH VOL Parameter Output supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 3.0 VR E F - 0.05 1.3 VR E F + 0.2 -0.3 Typical 3.3 VR E F 1.5 Maximum 3.6 VR E F + 0.05 1.7 VCCIO + 0.3 VR E F - 0.2 Unit V V V V V V IOH = -8 mA (9) IOL = 8 mA (9) VTT + 0.6 VT T - 0.6 V Altera Corporation May 2003 4-5 Preliminary Cyclone Device Handbook, Volume 1 Table 4-14. SSTL-3 Class II Specifications Symbol VCCIO VTT VREF VIH VIL VOH VOL Parameter Output supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions Minimum 3.0 VR E F - 0.05 1.3 VR E F + 0.2 -0.3 Typical 3.3 VR E F 1.5 Maximum 3.6 VR E F + 0.05 1.7 VCCIO + 0.3 VR E F - 0.2 Unit V V V V V V IOH = -16 mA (9) IOL = 16 mA (9) VT T + 0.8 VTT - 0.8 V Table 4-15. Bus Hold Parameters VC C I O Level Parameter Conditions 1.5 V Min Low sustaining current VIN > VIL (maximum) 1.8 V Min 30 -30 200 -200 2.5 V Min 50 -50 300 -300 3.3 V Min 70 -70 500 -500 Unit Max Max Max Max A A A A High sustaining VIN < VIH current (minimum) Low overdrive current High overdrive current 0 V < VIN < VCCIO 0 V < VIN < VCCIO 4-6 Preliminary Altera Corporation May 2003 Operating Conditions Table 4-16. Cyclone Device Capacitance Symbol CIO CLVDS CVREF CDPCLK CCLK (1) (2) Note (11) Typical 4.0 4.7 12.0 4.4 4.7 Parameter Input capacitance for user I/O pin Input capacitance for dual-purpose LVDS/user I/O pin Input capacitance for dual-purpose VR E F /user I/O pin. Input capacitance for dual-purpose DPCLK/user I/O pin. Input capacitance for CLK pin. Unit pF pF pF pF pF Notes to Tables 4-1 through 4-16: See the Operating Requirements for Altera Devices Data Sheet. Conditions beyond those listed in Table 4-1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) Minimum DC input is -0.5 V. During transitions, the inputs may undershoot to -0.5 V or overshoot to 4.6 V for input currents less than 100 mA and periods shorter than 20 ns. (4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically. (5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are powered. (6) Typical values are for TA = 25 C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V. (7) This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO settings (3.3, 2.5, 1.8, and 1.5 V). (8) Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO. (9) Drive strength is programmable according to values in Table 4-14. (10) The Cyclone LVDS interface requires a resistor network outside of the transmitter channels. (11) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within 0.5 pF. Altera Corporation May 2003 4-7 Preliminary Cyclone Device Handbook, Volume 1 Power Consumption Designers can use the Altera web power calculator to estimate the device power. Cyclone devices require a certain amount of power-up current to successfully power up because of the nature of the leading-edge process on which they are fabricated. Table 4-17 shows the maximum power-up current required to power up a Cyclone device. Table 4-17. Cyclone Power-Up Current (ICCINT) Requirements Device EP1C3 EP1C4 (1) EP1C6 (2) EP1C12 EP1C20 Notes to Table 4-17: (1) (2) The EP1C4 maximum power-up current is an estimated specification and may change. The EP1C6 maximum power-up current is for all EP1C6 devices except for those with lot codes listed in the Cyclone FPGA Family Errata Sheet. Maximum Power-Up Current Requirement 300 400 500 900 1,200 Unit mA mA mA mA mA Designers should select power supplies and regulators that can supply this amount of current when designing with Cyclone devices. This specification is for commercial operating conditions. Measurements were performed with an isolated Cyclone device on the board. Decoupling capacitors were not used in this measurement. To factor in the current for decoupling capacitors, sum up the current for each capacitor using the following equation: I = C (dV/dt) The exact amount of current that will be consumed varies according to the process, temperature, and power ramp rate. If the power supply or regulator can supply more current than required, the Cyclone device may consume more current than the maximum current specified in Table 4-17. However, the device does not require any more current to successfully power up than what is listed in Table 4-17. 4-8 Preliminary Altera Corporation May 2003 Timing Model The duration of the ICCINT power-up requirement depends on the VCCINT voltage supply rise time. The power-up current consumption drops when the VCCINT supply reaches approximately 0.75 V. For example, if the VCCINT rise time has a linear rise of 15 ms, the current consumption spike will drop by 7.5 ms. Typically, the user-mode current during device operation is lower than the power-up current in Table 4-17. Altera recommends using the Cyclone Power Calculator, available on the Altera web site, to estimate the user-mode ICCINT consumption and then select power supplies or regulators based on the higher value. Timing Model The DirectDrive technology and MultiTrack interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all Cyclone device densities and speed grades. This section describes and specifies the performance, internal, external, and PLL timing specifications. All specifications are representative of worst-case supply voltage and junction temperature conditions. Preliminary & Final Timing Timing models can have either preliminary or final status. The Quartus II software issues an informational message during the design compilation if the timing models are preliminary. Table 4-18 shows the status of the Cyclone device timing models. Preliminary status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible. Final timing numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under worstcase voltage and junction temperature conditions. Table 4-18. Cyclone Device Timing Model Status (Part 1 of 2) Device EP1C3 EP1C4 EP1C6 Preliminary v v v Final Altera Corporation May 2003 4-9 Preliminary Cyclone Device Handbook, Volume 1 Table 4-18. Cyclone Device Timing Model Status (Part 2 of 2) Device EP1C12 EP1C20 Preliminary v v Final Internal Timing Parameters Internal timing parameters are specified on a speed grade basis independent of device density. Tables 4-19 through 4-22 describe the Cyclone device internal timing microparameters for LEs, IOEs, M4K memory structures, and MultiTrack interconnects. Table 4-19. LE Internal Timing Microparameter Descriptions Symbol tSU tH tCO tLUT tCLR tPRE tCLKHL Parameter LE register setup time before clock LE register hold time after clock LE register clock-to-output delay LE combinatorial LUT delay for data-in to data-out Minimum clear pulse width Minimum preset pulse width Minimum clock high or low time Table 4-20. IOE Internal Timing Microparameter Descriptions Symbol tSU tH tCO tPIN2COMBOUT_R tPIN2COMBOUT_C tCOMBIN2PIN_R tCOMBIN2PIN_C tCLR tPRE tCLKHL Parameter IOE input and output register setup time before clock IOE input and output register hold time after clock IOE input and output register clock-to-output delay Row input pin to IOE combinatorial output Column input pin to IOE combinatorial output Row IOE data input to combinatorial output pin Column IOE data input to combinatorial output pin Minimum clear pulse width Minimum preset pulse width Minimum clock high or low time 4-10 Preliminary Altera Corporation May 2003 Timing Model Table 4-21. M4K Block Internal Timing Microparameter Descriptions Symbol tM4KRC tM4KWC tM4KWERESU tM4KWEREH tM4KBESU tM4KBEH tM4KDATAASU tM4KDATAAH tM4KADDRASU tM4KADDRAH tM4KDATABSU tM4KDATABH tM4KADDRBSU tM4KADDRBH tM4KDATACO1 tM4KDATACO2 tM4KCLKHL tM4KCLR Parameter Synchronous read cycle time Synchronous write cycle time Write or read enable setup time before clock Write or read enable hold time after clock Byte enable setup time before clock Byte enable hold time after clock A port data setup time before clock A port data hold time after clock A port address setup time before clock A port address hold time after clock B port data setup time before clock B port data hold time after clock B port address setup time before clock B port address hold time after clock Clock-to-output delay when using output registers Clock-to-output delay without output registers Minimum clock high or low time Minimum clear pulse width Table 4-22. Routing Delay Internal Timing Microparameter Descriptions Symbol tR4 tC4 tLOCAL Parameter Delay for an R4 line with average loading; covers a distance of four LAB columns Delay for an C4 line with average loading; covers a distance of four LAB rows Local interconnect delay Altera Corporation May 2003 4-11 Preliminary Cyclone Device Handbook, Volume 1 Figure 4-1 shows the memory waveforms for the M4K timing parameters shown in Table 4-21. Figure 4-1. Dual-Port RAM Timing Microparameter Waveform wrclock tWEREH wren tWADDRSU wraddress an-1 tDATAH data-in din-1 tDATASU rdclock tWERESU rden tRC rdaddress bn b0 tDATACO1 reg_data-out doutn-2 doutn-1 tDATACO2 unreg_data-out doutn-1 doutn dout0 doutn dout0 b1 b2 b3 tWEREH din din4 din5 din6 an a0 a1 a2 a3 a4 tWADDRH a5 a6 tWERESU Internal timing parameters are specified on a speed grade basis independent of device density. Tables 4-23 through 4-26 show the internal timing microparameters for LEs, IOEs, TriMatrix memory structures, DSP blocks, and MultiTrack interconnects. Table 4-23. LE Internal Timing Microparameters (Part 1 of 2) -6 Symbol Min tSU tH tCO tLUT 29 12 173 454 -7 Max Min 33 13 198 522 -8 Unit Max Min 37 15 224 590 Max ps ps ps ps 4-12 Preliminary Altera Corporation May 2003 Timing Model Table 4-23. LE Internal Timing Microparameters (Part 2 of 2) -6 Symbol Min tCLR tPRE tCLKHL 129 129 107 -7 Max Min 148 148 123 -8 Unit Max Min 167 167 139 Max ps ps ps Table 4-24. IOE Internal Timing Microparameters -6 Symbol Min tSU tH tCO tPIN2COMBOUT_R tPIN2COMBOUT_C tCOMBIN2PIN_R tCOMBIN2PIN_C tCLR tPRE tCLKHL 280 280 95 98 65 161 1,107 1,112 2,776 2,764 308 308 104 -7 Max Min 107 71 177 1,217 1,223 3,053 3,040 336 336 114 -8 Unit Max Min 117 78 193 1,328 1,334 3,331 3,316 Max ps ps ps ps ps ps ps ps ps ps Table 4-25. M4K Block Internal Timing Microparameters (Part 1 of 2) -6 Symbol Min tM4KRC tM4KWC tM4KWERESU tM4KWEREH tM4KBESU tM4KBEH tM4KDATAASU tM4KDATAAH 72 43 72 43 72 43 -7 Max 4,379 2,910 82 49 82 49 82 49 -8 Unit Max 5,035 3,346 93 55 93 55 93 55 Min Min Max 5,691 3,783 ps ps ps ps ps ps ps ps Altera Corporation May 2003 4-13 Preliminary Cyclone Device Handbook, Volume 1 Table 4-25. M4K Block Internal Timing Microparameters (Part 2 of 2) -6 Symbol Min tM4KADDRASU tM4KADDRAH tM4KDATABSU tM4KDATABH tM4KADDRBSU tM4KADDRBH tM4KDATACO1 tM4KDATACO2 tM4KCLKHL tM4KCLR 105 286 72 43 72 43 72 43 621 4,351 120 328 -7 Max Min 82 49 82 49 82 49 714 5,003 136 371 -8 Unit Max Min 93 55 93 55 93 55 807 5,656 Max ps ps ps ps ps ps ps ps ps ps Table 4-26. Routing Delay Internal Timing Microparameters -6 Symbol Min tR4 tC4 tLOCAL -7 Max 261 338 244 -8 Unit Max 300 388 281 Min Min Max 339 439 318 ps ps ps External Timing Parameters External timing parameters are specified by device density and speed grade. Figure 4-2 shows the timing model for bidirectional IOE pin timing. All registers are within the IOE. 4-14 Preliminary Altera Corporation May 2003 Timing Model Figure 4-2. External Timing in Cyclone Devices OE Register D PRN Q Dedicated Clock CLRN Output Register D PRN Q tXZ tZX tINSU tINH tOUTCO Bidirectional Pin CLRN Input Register PRN D Q CLRN All external I/O timing parameters shown are for 3.3-V LVTTL I/O standard with the maximum current strength and fast slew rate. For external I/O timing using standards other than LVTTL or for different current strengths, use the I/O standard input and output delay adders in Tables 4-38 through 4-42. Table 4-27 shows the external I/O timing parameters when using global clock networks. Table 4-27. Cyclone Global Clock External I/O Timing Parameters Symbol tI N S U tI N H tO U T C O tX Z tZ X tI N S U P L L Notes (1), (2) (Part 1 of 2) Conditions Parameter Setup time for input or bidirectional pin using IOE input register with global clock fed by CLK pin Hold time for input or bidirectional pin using IOE input register with global clock fed by CLK pin Clock-to-output delay output or bidirectional pin using IOE output register with global clock fed by CLK pin Synchronous column IOE output enable register to output pin disable delay using global clock fed by CLK pin Synchronous column IOE output enable register to output pin enable delay using global clock fed by CLK pin Setup time for input or bidirectional pin using IOE input register with global clock fed by Enhanced PLL with default phase setting CLOAD = 10 pF CLOAD = 10 pF CLOAD = 10 pF Altera Corporation May 2003 4-15 Preliminary Cyclone Device Handbook, Volume 1 Table 4-27. Cyclone Global Clock External I/O Timing Parameters Symbol tI N H P L L Notes (1), (2) (Part 2 of 2) Conditions Parameter Hold time for input or bidirectional pin using IOE input register with global clock fed by enhanced PLL with default phase setting Clock-to-output delay output or bidirectional pin using IOE output register with global clock enhanced PLL with default phase setting Synchronous column IOE output enable register to output pin disable delay using global clock fed by enhanced PLL with default phase setting Synchronous column IOE output enable register to output pin enable delay using global clock fed by enhanced PLL with default phase setting tO U T C O P L L CLOAD = 10 pF tX Z P L L CLOAD = 10 pF tZ X P L L CLOAD = 10 pF Notes to Table 4-27: (1) (2) These timing parameters are sample-tested only. These timing parameters are for IOE pins using a 3.3-V LVTTL, 24-mA setting. Designers should use the Quartus II software to verify the external timing for any pin. Tables 4-28 through 4-29 show the external timing parameters on column and row pins for EP1C3 devices. Table 4-28. EP1C3 Column Pin Global Clock External I/O Timing Parameters -6 Speed Grade Symbol Min tI N S U tI N H tO U T C O tX Z tZ X tI N S U P L L tI N H P L L tO U T C O P L L tX Z P L L tZ X P L L 1.195 0.000 0.500 1.900 3.527 3.527 2.496 0.000 2.000 3.656 5.283 5.283 1.308 0.000 0.500 2.094 3.885 3.885 -7 Speed Grade Min 2.715 0.000 2.000 4.049 5.840 5.840 -8 Speed Grade Unit Min 2.935 0.000 2.000 4.445 6.398 6.398 1.421 0.000 0.500 2.291 4.244 4.244 Max Max Max ns ns ns ns ns ns ns ns ns ns 4-16 Preliminary Altera Corporation May 2003 Timing Model Table 4-29. EP1C3 Row Pin Global Clock External I/O Timing Parameters -6 Speed Grade Symbol Min tI N S U tI N H tO U T C O tX Z tZ X tI N S U P L L tI N H P L L tO U T C O P L L tX Z P L L tZ X P L L 1.273 0.000 0.500 1.805 3.391 3.391 2.574 0.000 2.000 3.561 5.147 5.147 1.399 0.000 0.500 1.984 3.729 3.729 -7 Speed Grade Min 2.806 0.000 2.000 3.939 5.684 5.684 -8 Speed Grade Unit Min 3.041 0.000 2.000 4.319 6.223 6.223 1.527 0.000 0.500 2.165 4.069 4.069 Max Max Max ns ns ns ns ns ns ns ns ns ns Tables 4-30 through 4-31 show the external timing parameters on column and row pins for EP1C4 devices. Table 4-30. EP1C4 Column Pin Global Clock External I/O Timing Parameters Note (1) -6 Speed Grade Symbol Min tI N S U tI N H tO U T C O tX Z tZ X tI N S U P L L tI N H P L L tO U T C O P L L tX Z P L L tZ X P L L -7 Speed Grade Min Max -8 Speed Grade Unit Min Max ns ns ns ns ns ns ns ns ns ns Max Altera Corporation May 2003 4-17 Preliminary Cyclone Device Handbook, Volume 1 Table 4-31. EP1C4 Row Pin Global Clock External I/O Timing Parameters (1) -6 Speed Grade Symbol Min tI N S U tI N H tO U T C O tX Z tZ X tI N S U P L L tI N H P L L tO U T C O P L L tX Z P L L tZ X P L L Note to Tables 4-30 and 4-31: (1) Contact Altera Applications for EP1C4 device timing parameters. -7 Speed Grade Min Max -8 Speed Grade Unit Min Max ns ns ns ns ns ns ns ns ns ns Max Tables 4-32 through 4-33 show the external timing parameters on column and row pins for EP1C6 devices. Table 4-32. EP1C6 Column Pin Global Clock External I/O Timing Parameters -6 Speed Grade Symbol Min tI N S U tI N H tO U T C O tX Z tZ X tI N S U P L L tI N H P L L tO U T C O P L L tX Z P L L tZ X P L L 1.188 0.000 0.500 1.907 3.534 3.534 2.432 0.000 2.000 3.720 5.347 5.347 1.301 0.000 0.500 2.101 3.892 3.892 -7 Speed Grade Min 2.643 0.000 2.000 4.121 5.912 5.912 -8 Speed Grade Unit Min 2.853 0.000 2.000 4.527 6.480 6.480 1.414 0.000 0.500 2.298 4.251 4.251 Max Max Max ns ns ns ns ns ns ns ns ns ns 4-18 Preliminary Altera Corporation May 2003 Timing Model Table 4-33. EP1C6 Row Pin Global Clock External I/O Timing Parameters -6 Speed Grade Symbol Min tI N S U tI N H tO U T C O tX Z tZ X tI N S U P L L tI N H P L L tO U T C O P L L tX Z P L L tZ X P L L 1.273 0.000 0.500 1.805 3.391 3.391 2.517 0.000 2.000 3.618 5.204 5.204 1.399 0.000 0.500 1.984 3.729 3.729 -7 Speed Grade Min 2.741 0.000 2.000 4.004 5.749 5.749 -8 Speed Grade Unit Min 2.966 0.000 2.000 4.394 6.298 6.298 1.527 0.000 0.500 2.165 4.069 4.069 Max Max Max ns ns ns ns ns ns ns ns ns ns Tables 4-34 through 4-35 show the external timing parameters on column and row pins for EP1C12 devices. Table 4-34. EP1C12 Column Pin Global Clock External I/O Timing Parameters -6 Speed Grade Symbol Min tI N S U tI N H tOU T C O tX Z tZ X tI N S U P L L tI N H P L L tO U T C O P L L tX Z P L L tZ X P L L 1.152 0.000 0.500 1.943 3.570 3.570 2.187 0.000 2.000 3.965 5.592 5.592 1.260 0.000 0.500 2.142 3.933 3.933 -7 Speed Grade Min 2.363 0.000 2.000 4.401 6.192 6.192 -8 Speed Grade Unit Min 2.535 0.000 2.000 4.845 6.798 6.798 1.368 0.000 0.500 2.344 4.297 4.297 Max Max Max ns ns ns ns ns ns ns ns ns ns Altera Corporation May 2003 4-19 Preliminary Cyclone Device Handbook, Volume 1 Table 4-35. EP1C12 Row Pin Global Clock External I/O Timing Parameters -6 Speed Grade Symbol Min tI N S U tI N H tO U T C O tX Z tZ X tI N S U P L L tI N H P L L tO U T C O P L L tX Z P L L tZ X P L L 1.273 0.000 0.500 1.805 3.391 3.391 2.308 0.000 2.000 3.827 5.413 5.413 1.399 0.000 0.500 1.984 3.729 3.729 -7 Speed Grade Min 2.502 0.000 2.000 4.243 5.988 5.988 -8 Speed Grade Unit Min 2.694 0.000 2.000 4.666 6.570 6.570 1.527 0.000 0.500 2.165 4.069 4.069 Max Max Max ns ns ns ns ns ns ns ns ns ns Tables 4-36 through 4-37 show the external timing parameters on column and row pins for EP1C20 devices. Table 4-36. EP1C20 Column Pin Global Clock External I/O Timing Parameters -6 Speed Grade Symbol Min tI N S U tI N H tO U T C O tX Z tZ X tI N S U P L L tI N H P L L tO U T C O P L L tX Z P L L tZ X P L L 1.138 0.000 0.500 1.957 3.584 3.584 2.226 0.000 2.000 3.926 5.553 5.553 1.244 0.000 0.500 2.158 3.949 3.949 -7 Speed Grade Min 2.406 0.000 2.000 4.358 6.149 6.149 -8 Speed Grade Unit Min 2.585 0.000 2.000 4.795 6.748 6.748 1.349 0.000 0.500 2.363 4.316 4.316 Max Max Max ns ns ns ns ns ns ns ns ns ns 4-20 Preliminary Altera Corporation May 2003 Timing Model Table 4-37. EP1C20 Row Pin Global Clock External I/O Timing Parameters -6 Speed Grade Symbol Min tI N S U tI N H tO U T C O tX Z tZ X tI N S U P L L tI N H P L L tO U T C O P L L tX Z P L L tZ X P L L 1.273 0.000 0.500 1.805 3.391 3.391 2.361 0.000 2.000 3.774 5.360 5.360 1.399 0.000 0.500 1.984 3.729 3.729 -7 Speed Grade Min 2.561 0.000 2.000 4.184 5.929 5.929 -8 Speed Grade Unit Min 2.763 0.000 2.000 4.597 6.501 6.501 1.527 0.000 0.500 2.165 4.069 4.069 Max Max Max ns ns ns ns ns ns ns ns ns ns External I/O Delay Parameters External I/O delay timing parameters for I/O standard input and output adders and programmable input and output delays are specified by speed grade independent of device density. Tables 4-38 through 4-43 show the adder delays associated with column and row I/O pins for all packages. If an I/O standard is selected other than LVTTL 24 mA with a fast slew rate, add the selected delay to the external tCO and tSU I/O parameters shown in Tables 4-23 through 4-26. Table 4-38. Cyclone I/O Standard Column Pin Input Delay Adders (Part 1 of 2) -6 Speed Grade I/O Standard Min LVCMOS 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL SSTL-3 class I SSTL-3 class II SSTL-2 class I -7 Speed Grade Min Max 0 0 30 235 358 -244 -244 -291 -8 Speed Grade Unit Min Max 0 0 33 256 391 -266 -266 -317 ps ps ps ps ps ps ps ps Max 0 0 28 214 326 -221 -221 -264 Altera Corporation May 2003 4-21 Preliminary Cyclone Device Handbook, Volume 1 Table 4-38. Cyclone I/O Standard Column Pin Input Delay Adders (Part 2 of 2) -6 Speed Grade I/O Standard Min SSTL-2 class II LVDS -7 Speed Grade Min Max -291 -217 -8 Speed Grade Unit Min Max -317 -237 ps ps Max -264 -197 Table 4-39. Cyclone I/O Standard Row Pin Input Delay Adders -6 Speed Grade I/O Standard Min LVCMOS 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL 3.3-V PCI (1) SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II LVDS -7 Speed Grade Min Max 0 0 30 235 358 0 -244 -244 -291 -291 -217 -8 Speed Grade Unit Min Max 0 0 33 256 391 0 -266 -266 -317 -317 -237 ps ps ps ps ps ps ps ps ps ps ps Max 0 0 28 214 326 0 -221 -221 -264 -264 -197 Table 4-40. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2) -6 Speed Grade Standard Min LVCMOS 2 mA 4 mA 8 mA 12 mA 3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 24 mA -7 Speed Grade Min Max 1,216 661 151 0 1,216 814 143 196 0 -8 Speed Grade Unit Min Max 1,326 721 164 0 1,326 888 156 213 0 ps ps ps ps ps ps ps ps ps Max 1,105 601 137 0 1,105 740 130 178 0 4-22 Preliminary Altera Corporation May 2003 Timing Model Table 4-40. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 2 of 2) -6 Speed Grade Standard Min 2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA 1.8-V LVTTL 2 mA 8 mA 12 mA 1.5-V LVTTL 2 mA 4 mA 8 mA SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II LVDS -7 Speed Grade Min Max 1,654 338 372 214 1,168 893 893 2,812 1,774 1,170 678 198 581 256 162 -8 Speed Grade Unit Min Max 1,804 368 405 234 1,274 974 974 3,067 1,935 1,276 739 216 633 279 176 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps Max 1,504 307 338 195 1,062 812 812 2,556 1,613 1,064 616 180 528 233 147 Table 4-41. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 1 of 2) -6 Speed Grade Standard Min LVCMOS 2 mA 4 mA 8 mA 12 mA 3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 24 mA 2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA -7 Speed Grade Min Max 1,216 661 151 0 1,216 814 143 196 0 1,654 338 372 214 -8 Speed Grade Unit Min Max 1,326 721 164 0 1,326 888 156 213 0 1,804 368 405 234 ps ps ps ps ps ps ps ps ps ps ps ps ps Max 1,105 601 137 0 1,105 740 130 178 0 1,504 307 338 195 Altera Corporation May 2003 4-23 Preliminary Cyclone Device Handbook, Volume 1 Table 4-41. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 2 of 2) -6 Speed Grade Standard Min 1.8-V LVTTL 2 mA 8 mA 12 mA 1.5-V LVTTL 2 mA 4 mA 8 mA 3.3-V PCI (1) SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II LVDS -7 Speed Grade Min Max 2,812 1,168 893 2,812 1,774 1,170 -9 678 198 581 256 162 -8 Speed Grade Unit Min Max 3,067 1,274 974 3,067 1,935 1,276 -10 739 216 633 279 176 ps ps ps ps ps ps ps ps ps ps ps ps Max 2,556 1,062 812 2,556 1,613 1,064 -8 616 180 528 233 147 Table 4-42. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 1 of 2) -6 Speed Grade I/O Standard Min LVCMOS 2 mA 4 mA 8 mA 12 mA 3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 24 mA 2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA 1.8-V LVTTL 2 mA 8 mA 12 mA -7 Speed Grade Min Max 2,517 1,962 1,452 1,301 3,036 2,634 1,963 2,016 1,820 4,006 2,690 2,724 2,566 7,267 5,623 5,348 -8 Speed Grade Unit Min Max 2,745 2,140 1,583 1,419 3,312 2,874 2,142 2,199 1,986 4,370 2,934 2,971 2,800 7,927 6,134 5,834 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps Max 2,288 1,784 1,320 1,183 2,760 2,395 1,785 1,833 1,655 3,643 2,446 2,477 2,334 6,606 5,112 4,862 4-24 Preliminary Altera Corporation May 2003 Timing Model Table 4-42. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 2 of 2) -6 Speed Grade I/O Standard Min 1.5-V LVTTL 2 mA 4 mA 8 mA SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II LVDS -7 Speed Grade Min Max 9,218 8,180 7,576 1,979 1,499 2,326 2,001 1,463 -8 Speed Grade Unit Min Max 10,055 8,923 8,264 2,158 1,635 2,537 2,183 1,595 ps ps ps ps ps ps ps ps Max 8,380 7,437 6,888 1,799 1,363 2,115 1,820 1,330 Table 4-43. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 1 of 2) -6 Speed Grade I/O Standard Min LVCMOS 2 mA 4 mA 8 mA 12 mA 3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 24 mA 2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA 1.8-V LVTTL 2 mA 8 mA 12 mA 1.5-V LVTTL 2 mA 4 mA 8 mA 3.3-V PCI -7 Speed Grade Min Max 2,517 1,962 1,452 1,301 3,036 2,634 1,963 2,016 1,820 4,006 2,690 2,724 2,566 7,267 5,623 5,348 9,218 8,180 7,576 1,292 -8 Speed Grade Unit Min Max 2,745 2,140 1,583 1,419 3,312 2,874 2,142 2,199 1,986 4,370 2,934 2,971 2,800 7,927 6,134 5,834 10,055 8,923 8,264 1,409 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps Max 2,288 1,784 1,320 1,183 2,760 2,395 1,785 1,833 1,655 3,643 2,446 2,477 2,334 6,606 5,112 4,862 8,380 7,437 6,888 1,175 Altera Corporation May 2003 4-25 Preliminary Cyclone Device Handbook, Volume 1 Table 4-43. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 2 of 2) -6 Speed Grade I/O Standard Min SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II LVDS Note to Tables 4-38 through 4-43: (1) EP1C3 devices do not support the PCI I/O standard. -7 Speed Grade Min Max 1,979 1,499 2,326 2,001 1,463 -8 Speed Grade Unit Min Max 2,158 1,635 2,537 2,183 1,595 ps ps ps ps ps Max 1,799 1,363 2,115 1,820 1,330 Table 4-44 shows the adder delays for the IOE programmable delays. These delays are controlled with the Quartus II software options listed in the Parameter column. Table 4-44. Cyclone IOE Programmable Delays on Column Pins -6 Speed Grade Parameter Decrease input delay to internal cells -7 Speed Grade Min Max 3,362 2,433 2,902 3,362 3,362 607 -8 Speed Grade Unit Min Max 3,668 2,654 3,166 3,668 3,668 662 ps ps ps ps ps ps Setting Min On Small Medium Large Max 3,057 2,212 2,639 3,057 3,057 552 Decrease input delay to input register Increase delay to output pin On On 4-26 Preliminary Altera Corporation May 2003 Timing Model Table 4-45. Cyclone IOE Programmable Delays on Row Pins -6 Speed Grade Parameter Decrease input delay to internal cells -7 Speed Grade Min Max 3,362 2,433 2,902 3,362 3,362 611 -8 Speed Grade Unit Min Max 3,668 2,654 3,166 3,668 3,668 667 ps ps ps ps ps ps Setting Min On Small Medium Large Max 3,057 2,212 2,639 3,057 3,057 556 Decrease input delay to input register Increase delay to output pin On On Maximum Input & Output Clock Rates Tables 4-46 and 4-47 show the maximum input clock rate for column and row pins in Cyclone devices. Table 4-46. Cyclone Maximum Input Clock Rate for Column Pins I/O Standard LVTTL 2.5 V 1.8 V 1.5 V LVCMOS SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II LVDS -6 Speed Grade 304 220 213 166 304 100 100 134 134 231 -7 Speed Grade 304 220 213 166 304 100 100 134 134 231 -8 Speed Grade 304 220 213 166 304 100 100 134 134 231 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Table 4-47. Cyclone Maximum Input Clock Rate for Row Pins (Part 1 of 2) I/O Standard LVTTL 2.5 V -6 Speed Grade 304 220 -7 Speed Grade 304 220 -8 Speed Grade 304 220 Unit MHz MHz Altera Corporation May 2003 4-27 Preliminary Cyclone Device Handbook, Volume 1 Table 4-47. Cyclone Maximum Input Clock Rate for Row Pins (Part 2 of 2) I/O Standard 1.8 V 1.5 V LVCMOS SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II 3.3-V PCI (1) LVDS (1) -6 Speed Grade 213 166 304 100 100 134 134 66 231 -7 Speed Grade 213 166 304 100 100 134 134 66 231 -8 Speed Grade 213 166 304 100 100 134 134 66 231 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz Note to Tables 4-46 thorugh 4-47: EP1C3 devices do not support the PCI I/O standard. These parameters are only available on row I/O pins. Tables 4-48 and 4-49 show the maximum output clock rate for column and row pins in Cyclone devices. Table 4-48. Cyclone Maximum Output Clock Rate for Column Pins I/O Standard LVTTL 2.5 V 1.8 V 1.5 V LVCMOS SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II LVDS -6 Speed Grade 304 220 213 166 304 100 100 134 134 231 -7 Speed Grade 304 220 213 166 304 100 100 134 134 231 -8 Speed Grade 304 220 213 166 304 100 100 134 134 231 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 4-28 Preliminary Altera Corporation May 2003 Timing Model Table 4-49. Cyclone Maximum Output Clock Rate for Row Pins I/O Standard LVTTL 2.5 V 1.8 V 1.5 V LVCMOS SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II 3.3-V PCI (1) LVDS (1) -6 Speed Grade 304 220 213 166 304 100 100 134 134 66 231 -7 Speed Grade 304 220 213 166 304 100 100 134 134 66 231 -8 Speed Grade 304 220 213 166 304 100 100 134 134 66 231 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Note to Tables 4-48 through 4-49: EP1C3 devices do not support the PCI I/O standard. These parameters are only available on row I/O pins. Altera Corporation May 2003 4-29 Preliminary Cyclone Device Handbook, Volume 1 4-30 Preliminary Altera Corporation May 2003 5. Reference & Ordering Information C51005-1.0 Software Cyclone devices are supported by the Altera Quartus (R) II design software, which provides a comprehensive environment for system-on-aprogrammable-chip (SOPC) design. The Quartus (R) II software includes HDL and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, SignalTap II logic analysis, and device configuration. See the Design Software Selector Guide for more details on the Quartus (R) II software features. The Quartus (R) II software supports the Windows 2000/NT/98, Sun Solaris, Linux Red Hat v7.1 and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the NativeLink(R) interface. Device Pin-Outs Ordering Information Device pin-outs for Cyclone devices are available on the Altera web site (www.altera.com) and in the Cyclone FPGA Device Handbook. Figure 5-1 describes the ordering codes for Cyclone devices. For more information on a specific package, refer to Chapter 6, Package Information for Cyclone Devices. Figure 5-1. Cyclone Device Packaging Ordering Information EP1C Family Signature EP1C: Cyclone 20 F 400 C 7 ES Optional Suffix Indicates specific device options or shipment method. ES: Engineering sample Device Type 3 4 6 12 20 Speed Grade 6, 7, or 8 , with 6 being the fastest Operating Temperature Package Type T: Thin quad flat pack (TQFP) Q: Plastic quad flat pack (PQFP) F: FineLine BGA Pin Count Number of pins for a particular package C: Commercial temperature (tJ = 0 C to 85 C) I: Industrial temperature (tJ = -40 C to 100 C) Altera Corporation May 2003 5-1 Preliminary Cyclone Device Handbook, Volume 1 5-2 Preliminary Altera Corporation May 2003 Section II. Clock Management This section provides information on the Cyclone phase-lock loops (PLLs). The PLLs assist designers in managing clocks internally and also have the ability to drive off chip to control system-level clock networks. This chapter contains detailed information on the features, the interconnections to the logic array and off chip, and the specifications for Cyclone PLLs. This section contains the following: Chapter 6. Using PLLs in Cyclone Devices Revision History The table below shows the revision history for Chapter 6. Chapter(s) 6 Date / Version May 2003 v1.0 Changes Made Revised Table 6-1 with EP1C4. Updated Figure 6-8 and added information to Table 6-9 for fI N and fO U T. Altera Corporation Section II-1 Preliminary Clock Management Cyclone Device Handbook, Volume 1 Section II-2 Preliminary Altera Corporation 6. Using PLLs in Cyclone Devices C51006-1.0 Introduction CycloneTM FPGAs offer phase locked loops (PLLs) and a global clock network for clock management solutions. Cyclone PLLs offer clock multiplication and division, phase shifting, programmable duty cycle, and external clock outputs, allowing system-level clock management and skew control. The Altera(R) Quartus(R) II software enables Cyclone PLLs and their features without using any external devices. This application note explains how to design and enable Cyclone PLL features. PLLs are commonly used to synchronize internal device clocks with an external clock, run internal clocks at higher frequencies than an external clock, minimize clock delay and clock skew, and reduce or adjust clockto-out (TCO) and set-up (TSU) times. Hardware Overview Cyclone FPGAs contain up to two PLLs per device. Table 6-1 shows which PLLs are available for each Cyclone FPGA. Table 6-1. Cyclone FPGA PLL Availability Device EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 Notes to Table 6-1: (1) (2) Located on the center left side of the device. Located on the center right side of the device. PLL1 (1) v v v v v PLL2 (2) v v v v Altera Corporation May 2003 6-1 Preliminary Cyclone Device Handbook, Volume 1 Table 6-2 provides an overview of available Cyclone PLL features. Table 6-2. Cyclone PLL Features Feature Clock multiplication and division Phase shift Programmable duty cycle Number of internal clock outputs Number of external clock outputs (4) Locked port can feed logic array PLL clock outputs can feed logic array Notes to Table 6-2: (1) (2) (3) M counter values range from 2 to 32. N and post-scale counter values range from 1 to 32. The smallest phase shift is determined by the Voltage Control Oscillator (VCO) period divided by 8. For degree increments, Cyclone FPGAs can shift output frequencies in increments of at least 45. Smaller degree increments are possible depending on the multiplication/division ratio needed on the PLL clock output. The EP1C3 device in the 100-pin thin quad flat pack (TQFP) package does not have support for a PLL LVDS input or an external clock output. The EP1C6 PLL2 in the 144-pin TQFP package does not support an external clock output. Description M/(Nxpost-scale counter) (1) Down to 156-pico second (ps) increments (2), (3) v Two per PLL One per PLL v v (4) Cyclone PLL Blocks The main goal of a PLL is to synchronize the phase and frequency of an internal/external clock to an input reference clock. There are a number of components that comprise a PLL to achieve this phase alignment. Cyclone PLLs align the rising edge of the reference input clock to a feedback clock using a phase-frequency detector (PFD). The falling edges are determined by the duty cycle specifications. The PFD produces an up or down signal that determines whether the VCO needs to operate at a higher or lower frequency. The PFD output is applied to the charge pump and loop filter, which produces a control voltage for setting the frequency of the VCO. If the PFD produces an up signal, then the VCO frequency increases, while a down signal causes the VCO frequency to decrease. The PFD outputs these up and down signals to a charge pump. If the charge pump receives an up signal, current is driven into the loop filter. Conversely, if it receives a down signal, current is drawn from the loop filter. The loop filter converts these up and down signals to a voltage that 6-2 Preliminary Altera Corporation May 2003 Introduction is used to bias the VCO. The loop filter also removes glitches from the charge pump and prevents voltage over-shoot, which minimizes the jitter on the VCO. The voltage from the loop filter determines how fast the VCO operates. The VCO is implemented as a four-stage differential ring oscillator. A divide counter (M) is inserted in the feedback loop to increase the VCO frequency above the input reference frequency, making the VCO frequency (fVCO) equal to M times the input reference clock (fREF). The input reference clock (fREF) to the PFD is equal to the input clock (fIN) divided by the pre-scale counter (N). Therefore, the feedback clock (fFB) that is applied to one input of the PFD is locked to the fREF that is applied to the other input of the PFD. The VCO output can feed up to three post-scale counters (G0, G1, and E). These post-scale counters allow a number of harmonically-related frequencies to be produced within the PLL. Additionally, the PLL has internal delay elements to compensate for routing on the global clock networks and I/O buffers of the external clock output pins. These internal delays are fixed and not accessible to the user. Figure 6-1 shows a block diagram of the major components of a Cyclone PLL. Figure 6-1. Cyclone PLL VCO Phase Selection Selectable at each PLL Output Port Phase Frequency Detector fIN CLK(n) LVDSCLK1n (1), (2) CLK(n+1) /n PFD Charge Pump Loop Filter VCO fREF fVCO / g0 Global Clock Post-Scale Counters 8 / g1 Global Clock fFB /m /e I/O Buffer (3) Notes to Figure 6-1: (1) (2) The EP1C3 device in the 100-pin TQFP package does not have support for a PLL LVDS input. If you are using the LVDS standard, then both CLK pins of that PLL are used. LVDS input is supported via the secondary function of the dedicated CLK pins. For PLL1, the CLK0 pin's secondary function is LVDSCLK1p and the CLK1 pin's secondary function is LVDSCLK1n. For PLL2, the CLK2 pin's secondary function is LVDSCLK2p and the CLK3 pin's secondary function is LVDSCLK2n. The EP1C3 device in the 100-pin TQFP package, and the EP1C6 PLL2 in the 144-pin TQFP package do not support an external clock output. (3) Altera Corporation May 2003 6-3 Preliminary Cyclone Device Handbook, Volume 1 Software Overview Cyclone PLLs are enabled in the Quartus II software by using the altpll megafunction. Figure 6-2 shows the available ports (as they are named in the Quartus II altpll megafunction) of Cyclone PLLs and their sources and destinations. It is important to note that the c[1..0] and e0 clock output ports from altpll are driven by the post-scale counters G0, G1, and E (not necessarily in that order). The G0 and G1 counters feed the internal global clock network on the c0 and c1 PLL outputs, and the E counter feeds the PLL external clock output pin on the e0 PLL output. Figure 6-2. Cyclone PLL Signals (1) inclk0 (2) pllena areset pfdena c[1..0] (3) e0 locked (1) Physical pins Signal driven by internal logic Signal driven to internal logic Internal clock signal Notes to Figure 6-2: (1) (2) (3) You can assign these signals to either a single-ended I/O standard or LVDS. Inclk0 must be driven by the dedicated clock input pin(s). e0 drives the dual-purpose PLL[2..1]_OUT pins. 6-4 Preliminary Altera Corporation May 2003 Introduction Table 6-3 and 6-4 describe the Cyclone PLL input and output ports. Table 6-3. PLL Input Signals Port inclk0 Description Clock input to PLL. combined enable and reset signal for the PLL. You can use It for enabling or disabling one or two PLLs. When this signal is driven low, the PLL clock output ports are driven to GND and the PLL loses lock. Once this signal is driven high again, the lock process begins and the PLL re-synchronizes to its input reference clock. You can drive the pllena port from internal logic or any general-purpose I/O pin. Source Destination Dedicated clock input pin (1) /n counter PLL control signal pllena (2) pllena is an active-high signal that acts as a Logic array (3) areset areset is an active-high signal that resets all Logic array (3) PLL counters to their initial values. When this signal is driven high, the PLL resets its counters, clears the PLL outputs, and loses lock. Once this signal is driven low again, the lock process begins and the PLL resynchronizes to its input reference clock. You can drive the areset port from internal logic or any general-purpose I/O pin. PLL control signal pfdena pfdena is an active-high signal that enables or disables the up/down output signals from the PFD. When pfdena is driven low, the PFD is disabled, while the VCO continues to operate. The PLL clock outputs continue to toggle regardless of the input clock, but can experience some long-term drift. Because the output clock frequency does not change for some time, you can use the pfdena port as a shutdown or cleanup function when a reliable input clock is no longer available. You can drive the pfdena port from internal logic or any general-purpose I/O pin. Logic array (3) PFD Notes to Table 6-3: (1) (2) (3) The inclk0 port to the PLL must be driven by the dedicated clock input pin(s). There is no dedicated pllena pin for all PLLs, allowing you to choose either one pllena pin for both PLLs or each PLL can have its own pllena pin. Logic array source means that you can drive the port from internal logic or any general-purpose I/O pin. Altera Corporation May 2003 6-5 Preliminary Cyclone Device Handbook, Volume 1 Table 6-4. PLL Output Signals Port c[1..0] e0 (2) Description PLL clock outputs driving the internal global clock network. Source PLL post-scale counter G0 or G1 Destination Global clock network (1) PLL post-scale counter E PLL clock output driving the single-ended or LVDS external clock output pin(s). PLL lock detect Gives the status of the PLL lock. When the PLL is locked, this port drives logic high. When the PLL is out of lock, this port drives logic low. The locked port can pulse high and low during the PLL lock process. PLL[2..1]_OUT pin(s) (3) Logic array (4) locked Notes to Table 6-4: (1) (2) (3) (4) C[1..0] can also drive to any general-purpose I/O pin through the global clock network. The EP1C3 device in the 100-pin TQFP package, and the EP1C6 PLL2 in the 144-pin TQFP package do not have support for the external clock output PLL[2..1]_OUT. The PLL[2..1]_OUT pins are dual-purpose pins. If these pins are not required, they are available for use as general-purpose I/O pins. Logic array destination means that you can drive the port to internal logic or any general-purpose I/O pin. In the Quartus II software, you define which internal clock output from the PLL (c0 or c1) should be compensated. This PLL clock output is phase-aligned with respect to the PLL input clock. For example, if c0 is specified as the compensation clock in normal mode, the compensation is based on the c0 routing on the global clock network. Pins & Clock Network Connections You must drive Cyclone PLLs by the dedicated clock input pins CLK[3..0]. Inverted clocks and internally generated clocks cannot drive the PLL. Table 6-5 shows which dedicated clock pin drives which PLL input clock port. 6-6 Preliminary Altera Corporation May 2003 Introduction 1 A single clock input pin cannot drive both PLLs, but a single clock input pin can feed both registers in the logic array, as well as the PLL inclk port. Table 6-5. PLL Input Clock Sources Clock Input Pins (1) CLK0 CLK1 CLK2 CLK3 Notes to Table 6-5: (1) (2) If you are using the LVDS standard, then both CLK pins driving that PLL are used. The EP1C3 device only supports PLL1. PLL1 v v PLL2 (2) v v The c[1..0] and e0 clock output ports from altpll are driven by the PLL post-scale counters G0, G1, and E (not necessarily in that order). The G0 and G1 counters feed the internal global clock network on the c0 and c1 PLL outputs, and the E counter feeds the PLL external clock output pin on the e0 PLL output. Table 6-6 shows which global clock network can be driven by which PLL post-scale counter output. Table 6-6. PLL Output Clock Destinations onto the Global Clock Network PLL PLL 1 Counter Output G0 G1 GCLK0 GCLK1 v GCLK2 v GCLK3 GCLK4 GCLK5 GCLK6 GCLK7 v v v v v v PLL2 G0 G1 Figure 6-3 summarizes Table 6-5 and 6-6 by showing the PLL input and output clock connections. Altera Corporation May 2003 6-7 Preliminary Cyclone Device Handbook, Volume 1 Figure 6-3. Cyclone PLL Clock Connections GCLK1 GCLK3 GCLK0 GCLK2 GCLK5 GCLK7 GCLK4 GCLK6 CLK0 (1) CLK1 G0 G1 PLL 1 E CLK2 G0 G1 E PLL 2 PLL2_OUT (3) CLK3 (2) (3) PLL1_OUT Global Clocks Notes to Figure 6-3: (1) (2) (3) PLL1 supports one single-ended or LVDS input via the CLK0 and CLK1 pins. PLL2 supports one single-ended or LVDS input via the CLK2 and CLK3 pins. PLL1_OUT and PLL2_OUT support single-ended or LVDS outputs. If the external clock output is not required, these pins are available as general-purpose I/O pins. You can invert the clock outputs of the PLL at the logic array block (LAB) and at the input/output element (IOE) level. Hardware Features Cyclone PLLs have a number of advanced features available, including clock multiplication and division, phase shifting, programmable duty cycles, external clock outputs, and control signals. Clock Multiplication & Division Cyclone PLLs provide clock synthesis for PLL output ports using M/(N x post-scale) scaling factors. There is one pre-scale divider (N) and one multiply counter (M) per PLL. M counter values range from 2 to 32. N and post-scale counter values range from 1 to 32. The input clock (fIN) is divided by a pre-scale counter (N) to produce the input reference clock (fREF) to the PFD. fREF is then multiplied by the M feedback factor. The control loop drives the VCO frequency to match fIN x (M/N). See the following equations: fREF = fIN/N fVCO = fREF x M = fIN x (M/N) 6-8 Preliminary Altera Corporation May 2003 Hardware Features Each output port has a unique post-scale counter to divide down the high-frequency VCO. There are three post-scale counters (G0, G1, and E) that range from 1 to 32. See the following equations: fC0 = fVCO/G0 = fIN x (M/(N x G0)) fC1 = fVCO/G1 = fIN x (M/(N x G1)) fE = fVCO/E = fIN x (M/(N x E)) 1 c0 and c1 can use either post-scale counter, G0 or G1. For multiple PLL outputs with different frequencies, the VCO is set to the least common multiple of the output frequencies that meets the VCO frequency specifications. Then, the post-scale counters scale down the output frequency for each PLL clock output port. For example, if clock output frequencies required from one PLL are 33 and 66 MHz, the VCO is set to 330 MHz (the least common multiple in the VCO's range). Phase Shifting Cyclone PLLs have advanced clock shift capability to provide programmable phase shifting. You can enter the desired phase shift in the altpll MegaWizard(R) Plug-In Manager and the Quartus II software automatically sets and displays the closest phase shift achievable. You can enter the phase shift in degrees, or units of time, for each PLL clock output port. This feature is supported on all three PLL post-scale counters, G0, G1, and E and is supported for all available clock feedback modes. Phase shifting is performed with respect to the PLL clock output that is compensated. For example, you have a 100 MHz input clock and request a x 1 multiplication with a +90 phase shift on c0 and a x 1 multiplication with a +45 phase shift on c1. If you choose to compensate for the c0 clock output, the PLL uses a zero phase-shifted c0 clock as a reference point to produce the +90 phase shift on c0. Since c0 is the compensated clock, it is phase-shifted +90 from the input clock. The c1 clock also uses the zero phase-shifted c0 reference to produce the +45 phase shift on c1. For fine phase adjustment, each PLL clock output counter can choose a different phase of the VCO from up to eight phase taps. In addition, each clock output counter can use a unique initial count setting to achieve individual coarse phase shift selection, in steps of one VCO period. The Quartus II software can use this clock output counter, along with an initial setting on the post-scale counter, to achieve a phase shift range for the entire period of the output clock. You can phase shift the PLL clock output up to 180. The Quartus II software automatically sets the phase taps and counter settings according to the phase shift requested. Altera Corporation May 2003 6-9 Preliminary Cyclone Device Handbook, Volume 1 The resolution of the fine phase adjustment is dependent on the input frequency and the multiplication/division factors (i.e., it is a function of the VCO period), with the finest step being equal to an eighth ( x 0.125) of the VCO period. The minimum phase shift is 1/(8 x fVCO) or N/(8 x M x fIN). In Cyclone FPGAs, the VCO ranges from 300 to 800 MHz. Therefore, phase shifting can be performed with a resolution range of 1/(8 x 800 MHz) to 1/(8 x 300 MHz), which is 156 to 417 ps in time units. Because there are eight VCO phase taps, the maximum step size is 45. Smaller steps are possible, depending on the multiplication and division ratio necessary on the output clock port. The equation to determine the precision of the phase shifting in degrees is 45 divided by the post-scale counter value. For example, if you have an input clock of 125 MHz with x 1, the post-scale counter G0 is 3. Therefore, the smallest phase shift step is (45/3 = 15) and possible phase-shift values would be multiples of 15. This type of phase shift provides the highest precision since it is the least sensitive to process, voltage and temperature variation. Programmable Duty Cycle The programmable duty cycle feature allows you to set the duty cycle of the PLL clock outputs. The duty cycle is the ratio of the clock output high/low time to the total clock cycle time, which is expressed as a percentage of high time. This feature is supported on all three PLL postscale counters (G0, G1, and E). The duty cycle is set by using a low- and high-time count setting for the post-scale counters. The Quartus II software uses the input frequency and target multiply/divide ratio to select the post-scale counter. The precision of the duty cycle is determined by the post-scale counter value chosen on a PLL clock output and is defined as 50% divided by the postscale counter value. For example, if the post-scale counter value is 3, the allowed duty cycle precision would be 50% divided by 3 equaling 16.67%. Because the altpll megafunction does not accept non-integer values for the duty cycle values, the allowed duty cycles are 17, 33, 50, and 67%. Due to hard limitations, you cannot achieve a duty cycle of 84% because you cannot achieve the closest value to 100% for a given counter value. However, you can achieve a duty cycle of 84% by choosing a 17% duty cycle and inverting the PLL clock output. For example, if the G0 counter is 10, increments of 5% are possible for duty cycle choices between 5 and 90%. 6-10 Preliminary Altera Corporation May 2003 Hardware Features External Clock Output Each PLL supports one single-ended or LVDS external clock output for general-purpose external clocks, or for source-synchronous transmitters. The output of the E counter drives the PLL external clock output (e0), which can only feed to the PLL[2..1]_OUT pins and not to internal logic. You can use PLL[2..1]_OUT in all three clock feedback modes. 1 The EP1C3 device in the 100-pin package, and the EP1C6 PLL2 in the 144-pin package, do not have support for an external clock output. The PLL[2..1]_OUT pins are dual-purpose pins, meaning if the pins are not required by the PLL, they are available for use as general-purpose I/O pins. The I/O standards supported by the PLL[2..1]_OUT pins are listed in Table 6-7. Table 6-7. Supported I/O Standards for Cyclone PLL Pins I/O Standard LVTTL LVCMOS 2.5-V 1.8-V 1.5-V 3.3-V PCI LVDS (2) SSTL-2 Class I SSTL-2 Class II SSTL-3 Class I SSTL-3 Class II Differential SSTL-2 Class II Notes to Table 6-7: (1) (2) The EP1C3 device in the 100-pin TQFP package and the EP1C6 PLL2 in the 144-pin TQFP package do not support an external clock output. The EP1C3 device in the 100-pin TQFP package does not support an LVDS input. Inclk v v v v v v v v v v v PLL[2..1]_OUT (1) v v v v v v v v v v v v Since the pllena and locked signal can be driven by or driven to general-purpose I/O pins, respectively, they support all Cyclone I/O standards. Altera Corporation May 2003 6-11 Preliminary Cyclone Device Handbook, Volume 1 The Cyclone external clock output pins (PLL[2..1]_OUT) do not have a separate VCC and GND bank internal to the device. The PLL[2..1]_OUT pins share a VCCIO bank with neighboring I/O pins. Only the I/O pins in the same bank have an effect on the PLL[2..1]_OUT pins. Therefore, to minimize jitter on the PLL[2..1]_OUT pins, I/O pins directly adjacent to these pins should be either inputs or they should not be used. For more information about board design guidelines, see "Jitter Considerations" on page 6-19. Control Signals There are four available control signals, pllena, areset, pfdena, and locked, in Cyclone PLLs that provide added PLL management. pllena The PLL enable signal, pllena, enables or disables the PLL. When pllena is low, the PLL clock output ports are driven to logic low and the PLL loses lock. When pllena goes high again, the PLL relocks and resynchronizes to the input clock. Therefore, pllena is an active-high signal. In Cyclone FPGAs, you can feed the pllena port from internal logic or any general-purpose I/O pin because there is no dedicated pllena pin. This feature offers added flexibility, since each PLL can have its own pllena control circuitry, or both PLLs can share the same pllena circuitry. The pllena signal is optional, and when it is not enabled in the software, the port is internally tied to VCC. areset The PLL areset signal is the reset or resynchronization input for each PLL. When driven high, the PLL counters reset, clearing the PLL output and causing the PLL to lose lock. The VCO resets back to its nominal setting. When areset is again driven low, the PLL resynchronizes to its input clock as the PLL re-locks. If the target VCO frequency is below this nominal frequency, the PLL clock output frequency begins at a higher value than desired during the lock process. areset is an active-high signal. Cyclone FPGAs can drive this PLL input signal from internal logic or any general-purpose I/O pin. The areset signal is optional, and when it is not enabled in the software, the port is internally tied to GND. pfdena The pfdena signal controls the PFD output in the PLL with a programmable gate. If you disable the PFD by driving areset low, the VCO operates at its last set control voltage and frequency value with some long-term drift to a lower frequency. The VCO frequency can drift up to +/- 5% over 25 us. Even though the PLL clock outputs continue to 6-12 Preliminary Altera Corporation May 2003 Clock Feedback Modes toggle regardless of the input clock, the PLL could lose lock. The system continues running when the PLL goes out of lock, or if the input clock is disabled. Because the last locked output frequency does not change for some time, you can use the pfdena port as a shutdown or cleanup function when a reliable input clock is no longer available. By maintaining this frequency, the system has time to store its current settings before shutting down. If the pfdena signal goes high again, the PLL relocks and resynchronizes to the input clock. Therefore, the pfdena pin is an active-high signal. You can drive the pfdena input signal by any general-purpose I/O pin, or from internal logic. This signal is optional, and when it is not enabled in the software, the port is internally tied to VCC. locked When the locked output is at a logic-high level, this level indicates a stable PLL clock output in phase with the PLL reference input clock. Without any additional circuitry, the locked port may toggle as the PLL begins tracking the reference clock. The locked port of the PLL can feed any general-purpose I/O pin and/or internal logic. This locked signal is optional, but is useful in monitoring the PLL lock process. Clock Feedback Modes Cyclone PLLs support three feedback modes: normal, zero delay buffer, and no compensation. Unlike other Altera device families, Cyclone PLLs do not have support for external feedback mode. All three supported clock feedback modes allow for multiplication/division, phase shifting, and programmable duty cycle. The following sections give a brief description of each mode. 1 The phase relationship shown in Figure 6-4 through 6-6 are for the default phase shift setting of 0. Changing the phase-shift setting will change the relationships. Normal Mode In normal mode, the PLL phase aligns the input reference clock with the clock signal at the ports of the registers in the logic array or the IOE to compensate for the internal global clock network delay. In the altpll MegaWizard Plug-In Manager, you can define which internal clock output from the PLL (c0 or c1) should be compensated. If the external clock output (PLL[2..1]_OUT) is used in this mode, there will be a phase shift with respect to the clock input pin. Similarly, if you use the internal PLL clock outputs to drive general-purpose I/O pins, there will be a phase shift with respect to the clock input pin. Altera Corporation May 2003 6-13 Preliminary Cyclone Device Handbook, Volume 1 Figure 6-4 shows an example waveform of the PLL clocks' phase relationship in normal mode. Figure 6-4. Phase Relationship Between PLL Clocks in Normal Mode Phase Aligned PLL inclk PLL clock at the register clock port External PLL clock outputs (1) Note to Figure 6-4: (1) The external clock output can lead or lag the PLL clock signals. Zero Delay Buffer Mode The clock signal on the PLL external clock output pin (PLL[2..1]_OUT) is phase-aligned with the PLL input clock for zero delay. If you use the c[1..0] ports to drive internal clock ports, there will be a phase shift with respect to the input clock pin. Figure 6-5 shows an example waveform of the PLL clocks' phase relationship in zero delay buffer mode. 6-14 Preliminary Altera Corporation May 2003 Clock Feedback Modes Figure 6-5. Phase Relationship Between PLL Clocks in Zero Delay Buffer Mode Phase Aligned PLL inclk PLL clock at the register clock port External PLL clock outputs No Compensation In this mode, the PLL does not compensate for any clock networks, which leads to better jitter performance because the clock feedback into the PFD does not pass through as much circuitry. Both the PLL internal and external clock outputs are phase shifted with respect to the PLL clock input. Figure 6-6 shows an example waveform of the PLL clocks' phase relationship in no compensation mode. Altera Corporation May 2003 6-15 Preliminary Cyclone Device Handbook, Volume 1 Figure 6-6. Phase Relationship Between PLL Clocks in No Compensation Mode Phase Aligned PLL inclk PLL clock at the Register clock port (1) External PLL clock outputs Note to Figure 6-6: (1) Internal clocks fed by the PLL are in phase alignment with each other. Pins Table 6-8 describes the Cyclone PLL-related physical pins and their functionality. Table 6-8. Cyclone PLL Pins (Part 1 of 2) Pin Name CLK0 CLK1 (1) CLK2 CLK3 (1) PLL1_OUTp (2) PLL1_OUTn (2) PLL2_OUTp (2) PLL2_OUTn (2) VCCA_PLL1 (3) GNDA_PLL1 (4) VCCA_PLL2 (3) Description Single-ended or LVDS p-pin that can drive the inclk0 port of PLL1. Single-ended or LVDS n-pin that can drive the inclk0 port of PLL1. Single-ended or LVDS p-pin that can drive the inclk0 port of PLL2. Single-ended or LVDS n-pin that can drive the inclk0 port of PLL2. Single-ended or LVDS pins driven by the e0 port from PLL1. If not used by the PLL, these are available as general-purpose I/O pins. Single-ended or LVDS pins driven by the e0 port from PLL2. If not used by the PLL, these are available as general-purpose I/O pins. Analog power for PLL1. Even if the PLL is not used, you must connect this pin to 1.5 V. Analog ground for PLL1. You can connect this pin to the GND plane on the board. Analog power for PLL2. Even if the PLL is not used, you must connect this pin to 1.5 V. 6-16 Preliminary Altera Corporation May 2003 Board Layout Table 6-8. Cyclone PLL Pins (Part 2 of 2) Pin Name GNDA_PLL2 (4) GNDG_PLL1 (5) GNDG_PLL2 (5) Notes to Table 6-8: (1) (2) (3) (4) (5) The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins CLK1 and CLK3. The EP1C3 device in the 100-pin TQFP package, and the EP1C6 PLL2 in the 144-pin TQFP package do not support an external clock output. Refer to "Board Layout" on page 6-17 for filtering and other recommendations. The EP1C3 device in the 100-pin TQFP package, and the EP1C6 PLL2 in the 144-pin TQFP package do not have a separate GNDA_PLL pin. They are internally tied to GND. The Guard ring power (VCCG_PLL) is tied internally to VCCINT. Description Analog ground for PLL2. You can connect this pin to the GND plane on the board. Guard ring ground for PLL1. You can connect this pin to the GND plane on the board. Guard ring ground for PLL2. You can connect this pin to the GND plane on the board. Board Layout Cyclone PLLs contain analog components that are embedded in a digital device. These analog components have separate power and ground pins to provide immunity against noise generated by the digital components. These separate VCC and GND pins are used to isolate circuitry and improve noise resistance. VCCA & GNDA Each PLL has separate VCC and GND pairs for their analog circuitry. The analog circuit power and ground pin for each PLL is called VCCA_PLL# and GNDA_PLL# (# represents the PLL number). Even if the PLL is not used, the VCCA power must be connected to a 1.5-V supply. The power connected to VCCA must be isolated from the power to the rest of the Cyclone FPGA, or any other digital device on the board. The following sections describe three different methods for isolating VCCA. Separate VCCA Power Plane The designer of a mixed-signal system would have already partitioned the system into analog and digital sections, each with its own power planes on the board. In this case, you can connect VCCA to the analog 1.5V power plane. Partitioned VCCA Island within VCCINT Plane Most systems using Altera devices are fully digital, so there is not a separate analog power plane readily available on the board. Adding new planes to the board may be expensive. Therefore, you can create islands Altera Corporation May 2003 6-17 Preliminary Cyclone Device Handbook, Volume 1 for VCCA_PLL. The dielectric boundary that creates the island is approximately 25 mils thick. Figure 6-7 shows a partitioned plane within VCCINT for VCCA. Figure 6-7. VCCINT Plane Partitioned for VCCA Island Thick VCCA Traces Due to board restraints, it may not be possible to partition a VCCA island. Instead, run a thick trace from the power supply to each of the VCCA pins. The traces should be at least 20 mils thick. In all cases, each VCCA pin must be filtered with a decoupling circuit shown in Figure 6-8. You must place a ferrite bead and a 10-F tantalum parallel capacitor where the power enters the board. Choose a ferrite bead that exhibits high impedance at frequencies of 50 MHz or higher. Each VCCA pin must be decoupled with a 0.1-F and a 0.001-F parallel combination of ceramic capacitors, along with a series 1- resistor, 6-18 Preliminary Altera Corporation May 2003 Board Layout located as close as possible to the Cyclone FPGA. You can connect the GNDA pins directly to the same GND plane as the digital GND of the device. Figure 6-8. PLL Power Schematic for Cyclone PLLs Ferrite Bead 1.5-V Supply 10 F GND PLL<#>_VCCA -1 F .001 F PLL<#>_GNDA GND GND PLL<#>_GNDG GND Cyclone Device Repeat for each PLL power and ground set f For more information about board design guidelines, see Application Note 75: High-Speed Board Design. Jitter Considerations If the input clocks have any low-frequency jitter (below the PLL bandwidth), the PLL attempts to track it, which increases the jitter seen at the PLL clock output. To minimize this effect, avoid placing noisy signals in the same VCCIO bank as those that power the PLL clock input buffer. This is only important if the PLL input clock is assigned to 3.3-V or 2.5-V LVTTL or LVCMOS I/O standards. With these I/O standards, VCCIO Altera Corporation May 2003 6-19 Preliminary Cyclone Device Handbook, Volume 1 powers the input clock buffer. Therefore, any noise on this VCCIO supply can affect jitter performance. For all other I/O standards the input buffers are powered by VCCINT. Because Cyclone external clock output pins (PLL[2..1]_OUT) do not have a separate VCC and GND bank, you should avoid placing noisy output signals directly next to these pins. Therefore, Altera recommends that PLL[2..1]_OUT neighboring I/O pins should be either inputs pins or not used at all. If noisy outputs are placed next to the PLL[2..1]_OUT pins, they could inject noise through ground bounce or VCC sag and mutual pin inductance, which would result in worse jitter performance on the PLL[2..1]_OUT pins. Additionally, you should take into consideration the number of simultaneously switching outputs within the same VCCIO bank as the PLL[2..1]_OUT pins. Altera recommends that you switch as few outputs simultaneously in the same direction as possible in these VCCIO banks. Also, if you have switching outputs in the same VCCIO bank as the PLL[2..1]_OUT pins, Altera recommends that you use the low current strength and/or slow slew rate options on those output pins as they will help to improve the jitter performance. Specifications Table 6-9 describes the Cyclone FPGA PLL specifications. Table 6-9. Cyclone PLL Specifications Symbol fIN(-6 speed grade) fIN(-7 speed grade) fIN(-8 speed grade) fIN DUTY tIN JITTER fOUT(-6 speed grade) fOUT(-7 speed grade) fOUT(-8 speed grade) tOUT DUTY tJITTER (2) tLOCK Note (1) (Part 1 of 2) Min 15.00 15.00 15.00 40.00 200 181 166 60 Parameter Input frequency Input frequency Input frequency Input clock duty cycle Input clock jitter (peak-to-peak) PLL output frequency PLL output frequency PLL output frequency Duty cycle for external clock output (when set to 50%) PLL external clock output jitter (peak-to-peak) Time required to lock from end of device configuration 10.00 9.38 9.38 9.38 45.00 Max Unit MHz MHz MHz % ps MHz MHz MHz % ps s 200 312 283 260 55 TBD 100 6-20 Preliminary Altera Corporation May 2003 Software Support Table 6-9. Cyclone PLL Specifications Symbol fVCO M (3) N, G0, G1, E Notes to Table 6-9: (1) (2) Note (1) (Part 2 of 2) Min 300.00 2 1 Parameter PLL internal VCO operating range Counter values Counter values Max 800 32 32 Unit MHz integer integer (3) These numbers are preliminary and pending silicon characterization. The tJITTER specification for the PLL[2..1]_OUT pins are dependent on the I/O pins in its VCCIO bank, how many of them are switching outputs, how much they toggle, and whether or not they use programmable current strength or slow slew rate. M can only range from 2 - 32 because the maximum PLL input frequency is 200 MHz and the minimum VCO frequency is 300 MHz. Since fVCO = fIN x (M / N) there can never be a situation when M = 1 since that would violate the minimum VCO frequency specification. Software Support Support for Cyclone PLLs is available in the Quartus II software by using the altpll megafunction. The following section describes how the altpll megafunction enables the various Cyclone PLL features and options. This section includes the megafunction symbol, the input and output ports, a description of the MegaWizard Plug-In Manager options, and example MegaWizard screen shots. Quartus II altpll Megafunction Figure 6-9 shows the altpll megafunction symbol in the Quartus II software. Figure 6-9. altpll Megafunction Symbol Targeted for Cyclone FPGAs Altera Corporation May 2003 6-21 Preliminary Cyclone Device Handbook, Volume 1 f Refer to Quartus II Help for the altpll megafunction AHDL functional prototypes (applicable to Verilog HDL), VHDL component declaration, and parameter descriptions. altpll Input Ports Table 6-10 shows the input ports of the altpll megafunction and describes their function. Table 6-10. Input Ports of the altpll Megafunction Port Name inclk0 (1) pllena (2) Required Yes No Description The input clock port that drives the PLL. pllena is an active-high signal, which acts as a combined enable and reset signal for the PLL. You can use it for enabling or disabling one or both PLLs. When this signal is driven low, the PLL clock output ports are driven to GND and the PLL loses lock. Once this signal is driven high again, the lock process begins and the PLL re-synchronizes to its input reference clock. The pllena port can be driven from internal logic or any general-purpose I/O pin. areset is an active-high signal, which resets all PLL counters to their initial values. When this signal is driven high, the PLL resets its counters, clears the PLL outputs, and loses lock. Once this signal is driven low again, the lock process begins and the PLL re-synchronizes to its input reference clock. You can drive the areset port from internal logic or any general-purpose I/O pin. pfdena is an active-high signal, which enables or disables the up/down output signals from the PFD. When pfdena is driven low, the PFD is disabled, while the VCO continues to operate. PLL clock outputs continue to toggle regardless of the input clock, but can experience some long-term drift. Because the output clock frequency does not change for some time, you can use the pfdena port as a shutdown or cleanup function when a reliable input clock is no longer available. You can drive the pfdena port from internal logic or any general-purpose I/O pin. areset (2) No pfdena (2) No Notes to Table 6-10: (1) (2) The inclk0 port to the PLL must be driven by the dedicated clock input pin(s). See "Control Signals" on page 6-12 for further details. 6-22 Preliminary Altera Corporation May 2003 Software Support altpll Output Ports Table 6-11 shows the output ports of the altpll megafunction and describes their function. Table 6-11. Output Ports of the altpll Megafunction Port Name e0 (1) locked (2) Required No No Description Clock output of the PLL that drives the internal global clock network. Clock output that feeds the external clock output pins, PLL[2..1]_OUT. Gives the status of the PLL lock. When the PLL is locked, this port drives logic high. When the PLL is out of lock, this port drives logic low. The locked port can pulse high and low during the PLL lock process. c[1..0] (1) No Notes to Table 6-11: (1) (2) Either the internal or external clock output of the PLL must be selected. See "Control Signals" on page 6-12 for further details. MegaWizard Customization You can use the MegaWizard Plug-In Manager to set the altpll megafunction options for each PLL instance in your design. f If you instantiate the altpll megafunction without using the MegaWizard Plug-In Manager, search for "altpll" in the Quartus II Help for a list of the altpll parameters. In the MegaWizard Plug-In Manager, select the altpll megafunction in the I/O directory from the Available Megafunctions dialog box (see Figure 6-10). The altclklock megafunction is also available from the Quartus II software for backward compatibility, but instantiates the new altpll megafunction when targeting Cyclone FPGAs. Altera Corporation May 2003 6-23 Preliminary Cyclone Device Handbook, Volume 1 Figure 6-10. altpll Megafunction Selection in the MegaWizard Plug-In Manager The altpll MegaWizard Plug-In Manager has separate pages that apply to Cyclone PLLs. The MegaWizard will gray-out options that are unavailable in Cyclone PLLs. During compilation, the Quartus II Compiler verifies the altpll parameters selected against the available PLLs, and any PLL or input clock location assignments. At the top right-hand corner of each page of the altpll MegaWizard Plug-In Manager, there is a jump to page drop-down list (see Figure 6-11). This drop-down list allows you to jump to any particular altpll MegaWizard page and set those options. 6-24 Preliminary Altera Corporation May 2003 Software Support Figure 6-11. Jump to Page Drop-Down List in the altpll MegaWizard Plug-In MegaWizard Page Description This section describes the options available on the altpll MegaWizard pages. Each of the MegaWizard pages are shown. Tables 6-12 through 6-14 describe the features or settings on that page that apply to Cyclone PLLs. Use these tables, along with the hardware descriptions of the PLL features, to determine appropriate settings for your PLL instance. You can use the General/Modes (Page 1) of the altpll MegaWizard Plug-In Manager for selecting the target device family, clock input frequency, general control signal selection, and clock feedback operation mode (see Figure 6-12 and Table 6-12). Altera Corporation May 2003 6-25 Preliminary Cyclone Device Handbook, Volume 1 Figure 6-12. altpll MegaWizard Plug-In Manager (Page 1) Table 6-12. altpll MegaWizard Plug-In Options Page 1 (Part 1 of 2) Function Which device family will you be using? What is the frequency of the inclock0 input Create an pllena input to selectively enable the PLL Create an areset input to asynchronously reset the PLL Create an pfdena input to selectively enable the PFD Description This application note explains all altpll options that apply when Cyclone is the target device family selected. The frequency for the PLL input clock, inclock0. Creates a pllena port for this PLL instance. See Table 6-10 for pllena port description. Creates a areset port for this PLL instance. See Table 6-10 for areset port description. Creates a pfdena port for this PLL instance. See Table 6-10 for pfdena port description. 6-26 Preliminary Altera Corporation May 2003 Software Support Table 6-12. altpll MegaWizard Plug-In Options Page 1 (Part 2 of 2) Function Description Use the feedback path inside the This option sets the OPERATION_MODE parameter to either normal, zero PLL delay buffer, or no compensation mode. In normal mode, the PLL feedback path comes from a global clock network, which minimizes the clock delay to registers for that specific PLL clock output. You can specify which PLL output is compensated for by using the COMPENSATE_CLOCK parameter. In zero delay buffer mode, the PLL feedback path is confined to the dedicated PLL external output pin. The clock signal driven off-chip on the PLL_OUT pin is phase aligned with the PLL clock input for a minimized delay between clock input and external clock output. If the PLL is also used to drive the internal clock network, a corresponding phase shift of that clock network results. In no compensation mode, the PLL feedback path is confined to the PLL loop; it does not come from the global clock network or an external source. There is no clock network compensation, but this mode minimizes jitter on clocks. This mode may lead to positive hold times on IOE registers; you can use manual phase shifting to compensate for positive hold times. For more information, see "Clock Feedback Modes" on page 6-13. Which output clock will be compensated? Indicates which output port of the PLL is compensated. For normal mode, you can select c0 or c1. Altera Corporation May 2003 6-27 Preliminary Cyclone Device Handbook, Volume 1 You can use Scan/Lock (Page 2) for selecting the locked output port (see Figure 6-13 and Table 6-13). Figure 6-13. altpll MegaWizard Plug-In Manager (Page 2) Table 6-13. altpll MegaWizard Plug-In Options Page 2 Function Create "locked" output Description Creates a locked output port to indicate PLL lock. See locked port description in Table 6-11. The options on the next two pages of the MegaWizard Plug-In Manager, (Pages 3 to 4, titled Bandwidth/SS and Clock Switchover) are not supported in Cyclone FPGAs. 6-28 Preliminary Altera Corporation May 2003 Software Support Figure 6-14. altpll MegaWizard Plug-In Manager Pages 5 of 8 The last 3 pages of the MegaWizard Plug-In Manager (Pages 5 to 7) allow you to set the multiplication/division factors, phase shift, and duty cycle for each PLL output port (see Figure 6-14 and Table 6-14). Altera Corporation May 2003 6-29 Preliminary Cyclone Device Handbook, Volume 1 Each page represents the settings for one PLL clock output port. Table 6-14 describes the options for Pages 5 to 8. Table 6-14. altpll MegaWizard Plug-In Options Pages 5 of 8 Function Clock multiplication factor (ratio) Clock division factor (ratio) Clock phase shift (Ph) Description Specifies the clock multiplication for this PLL output. The multiplication factor cannot be greater than 32. Specifies the clock division for this PLL output. Sets the programmable phase shift for the clock output with respect to the PLL clock output that is compensated. The equation to determine the precision of the phase shifting in degrees is (45 divided by the post-scale counter value). Therefore, the maximum step size is 45, and smaller steps are possible, depending on the multiplication/division ratio necessary on the clock output port. For example, if you have an input clock of 125 MHz with x1, the post-scale counter G0 is 3. Therefore, the smallest phase shift step is 15, and additional phase shifting is in 15 increments. The up/down buttons cycle through the possible phase shift settings with the default M and post-scale dividers that the MegaWizard Pug-In Manager has chosen for your target frequency and multiplication/division ratio. It is possible to get other granularities of phase shifts if you manually enter a number into the phase shift field. For example, you can override the MegaWizard-chosen values and manually enter 7.5. The MegaWizard Plug-In Manager verifies this is possible by using M = 6 and G0 = 6. The MegaWizard Plug-In Manager tries to achieve the closest phase shift possible. For example, if you enter 10, the MegaWizard Plug-In Manager verifies that 9 is possible by using M = 5 and G0 = 5. For more information, see "Phase Shifting" on page 6-9. Clock duty cycle (DC) Specifies the clock duty cycle of the PLL clock output. The equation to determine the precision of the duty cycle is (50% divided by the post-scale counter value). For example, if post-scale counter G0 is 3, the allowed duty cycles are 50% divided by 3, equaling 16.67%. Because the altpll megafunction does not accept non-integer values for the duty cycle values, the allowed duty cycles are 17, 33, 50, and 67%. Due to hard limitations, a duty cycle of 84% cannot be achieved because the closest value to 100% cannot be achieved for a given counter value. However, you can achieve a duty cycle of 84% by choosing a 17% duty cycle and inverting the PLL clock output. Use the up/down buttons to cycle through all possible settings. For more information, see "Programmable Duty Cycle" on page 6-10. Page 8 is the summary page and tells you what files the MegaWizard Plug-In Manager will create (see Figure 6-15). 6-30 Preliminary Altera Corporation May 2003 Software Support 1 You can click Finish at anytime while in the MegaWizard PlugIn Manager to update the files. Figure 6-15. altpll MegaWizard Plug-In Manager Page 8 Compilation Report During compilation, an information message displays whether the requested multiplication/division factors, and/or phase shift, and/or duty cycle were achieved. If you enter an invalid multiplication/division ratio, compilation fails, and the Quartus II software displays an error message. If you enter an invalid phase shift or duty cycle value, the compilation proceeds, and you will receive an information message displaying the best alternative values chosen by the Quartus II software. The Resource Section of the compilation report provides two PLL reports: the PLL Summary and the PLL Usage reports. The PLL Summary provides information on each PLL's parameters (see Figure 6-16). The PLL Summary is column-based in the report file, where each column represents a different PLL instance. Table 6-15 lists and explains the parameters shown in the PLL Summary report. PLL properties not listed in Table 6-15 do not apply to Cyclone PLLs. Altera Corporation May 2003 6-31 Preliminary Cyclone Device Handbook, Volume 1 Figure 6-16. PLL Summary Report Table 6-15. PLL Summary in Compilation Report File (Part 1 of 2) PLL Property PLL mode Compensate clock Input frequency 0 Clock feedback mode Indicates which PLL clock output (clock0, clock1, or extclock0) port is compensated Clock input frequency for inclk0 Description 6-32 Preliminary Altera Corporation May 2003 Software Support Table 6-15. PLL Summary in Compilation Report File (Part 2 of 2) PLL Property Nominal VCO frequency Freq min lock Freq max lock M value N value Description Shows the VCO frequency; fVCO = fIN x M/N Shows the minimum PLL input clock frequency for which the current combination of M/N still provides a valid VCO lock Shows the maximum PLL input clock frequency for which the current combination of M/N still provides a valid VCO lock M counter value N counter value The PLL Usage report shows the breakdown information for each PLL clock output (see Figure 6-17). This report is categorized by PLL clock output ports, such that each row represents a different PLL clock output used in your design. Table 6-16 lists and explains the parameters shown in the PLL Usage report file in a row format. PLL parameters not listed in Table 6-16 do not apply to Cyclone PLLs. Figure 6-17. PLL Usage Report Timing Analysis Table 6-16 shows the usage in the compilation report file. Table 6-16. PLL Usage in Compilation Report File (Part 1 of 2) PLL Parameter Name Output Clock Description Indicates the PLL instance name and clock output reported. Indicates the PLL clock output (clock0, clock1, or extclock0) for which the parameter information in this row applies. This is the clock port specified in the MegaWizard Plug-In Manager (c0, c1, e0). Overall multiplication ratio. Overall division ratio. Output frequency for this output clock. Achieved phase shift in degrees and units of time (can differ from user-entered value). Mult Div Output Frequency Phase Shift Altera Corporation May 2003 6-33 Preliminary Cyclone Device Handbook, Volume 1 Table 6-16. PLL Usage in Compilation Report File (Part 2 of 2) PLL Parameter Duty Cycle Counter Counter Value High/Low Initial VCO Tap Duty cycle for this clock output. Post-scale counter used for this clock output, which counter (G0, G1, E0) feeds the clock output. Value of post-scale counter. High- and low-time counts that make up the counter value. The ratio of high- and low-counts is directly proportional to the duty cycle. Initial value for this post-scale counter (achieves the coarse granularity for phase shifting). Specifies the initial number of VCO cycles before starting the counter. VCO tap ranges from 0 to 7 (achieves fine granularity for phase shift in units of 1/8 of the VCO period). Description The register-to-register timing for each PLL clock output that drives the logic array is reported with slack. The timing analysis section of the report file provides slack information in a clock requirement line for each PLL clock output. You can derive fMAX numbers from the slack reporting. The microparameters tCO, tSU, and the path delay are given for a List Path command on the Actual Maximum P2P timing in the Slack Report window. You can add and invert these to find the fMAX for that path. See the following equation: fMAX = 1/( A warning during compilation reports that the project clock settings override the PLL clock settings. The project clock setting overrides the PLL clock settings for timingdriven compilation. When you compile a design with timing-driven compilation turned on, you are overconstraining the design so that the fitter can give you a better fMAX performance. For example, if the PLL is set to output a 150 MHz clock, you can set a project clock setting for 170 MHz so that the fitter tries to achieve a design performance of 170 MHz. 6-34 Preliminary Altera Corporation May 2003 Software Support The Compiler checks the lock frequency range of the PLL. If the frequency specified in the project clock settings is outside the lock frequency range, the PLL clock settings will not be overridden. Overriding the PLL clock settings only changes the timing requirements; it does not change the overall multiplication/division and phase delay on each clock output of the PLL. The MegaWizard Plug-In Manager does not use the project clock settings to determine the altpll parameters. Performing a timing analysis without recompiling your design does not change the programming files. You must recompile your design to update the programming files. A Default Required fMAX setting does not override the PLL clock settings. Only individual clock settings will override the PLL clock settings. This capability is useful when you have configured a Cyclone device and want to see if your timing requirements are met when you feed the PLL a different input clock than what is specified for the PLL parameters. Therefore, this feature allows you to overwrite the PLL input clock frequency settings for timing analysis, meaning you do not have to resynthesize or re-fit your design. The following procedure allows you to override the PLL input frequency setting and re-generate timing analysis. 1. 2. 3. Choose Timing Settings (Project menu). Click on the Clock Settings tab. Under Specify circuit frequency as, select Settings for individual clock signals. Click New. In the New Clock Settings dialog box, type a 4. 5. 6. b. Altera Corporation May 2003 6-35 Preliminary Cyclone Device Handbook, Volume 1 c. In the Duty Cycle list, specify the required duty cycle for the clock. Cyclone PLLs accept input clocks with 40 to 60% duty cycle. 1 d. If you want to include external delays to and from device pins in the fMAX calculations, turn on Include external delays to and from device pins in fMAX calculations. Click OK. e. 7. 8. 9. Click OK to close the Timing Settings window. Open the Assignment Organizer dialog box (Tools menu). Click on the By Node tab. 10. Under Mode, select Edit specific entity & node settings for. 11. If necessary, copy a specific PLL input clock pin name to the Name box using the Node Finder dialog box. 12. Under Assignment Categories, click the + icon next to Timing. 13. Click on Click here to add a new assignment. 14. Under Assignment, select Clock Settings in the Name list, and select the 6-36 Preliminary Altera Corporation May 2003 Software Support Simulation The altpll megafunction supports behavioral and timing simulation in both the Quartus II software and supported third-party simulation tools. You can simulate all digital aspects of the PLL, but none of the analog aspects. Simulation supports all control signals and clock outputs. Table 6-17 explains the simulation support for altpll. Table 6-17. altpll Simulation Support for Cyclone FPGAs Feature pllena areset Simulation Support The pllena signal is modeled. When this signal is driven low, the PLL loses lock and the PLL clock outputs are driven to logic low. The areset signal is modeled. When this signal is driven high, the PLL loses lock and the PLL clock outputs are driven to logic low. Frequency over-shoot on the PLL clock outputs is not modeled. The pfdena control signal is modeled. When this signal is driven low, the PLL's locked output is undefined and the PLL clock outputs continue to toggle at their last set frequency. The finite frequency long-term drift of the VCO is not modeled. The locked signal is modeled for a high-bandwidth condition only. The PLL locks or relocks within 2 to 10 cycles during simulation, and does not necessarily reflect the real lock time. If the input frequency of the PLL is changed in simulation, the model checks that fIN x (M/N) is within the VCO frequency range and loses lock if outside the VCO operating range. Jitter is not modeled in simulation. pfdena locked Frequency input change Jitter You can use the altpll behavioral model to simulate the Cyclone PLLs. The Cyclone behavioral model instantiation must follow the same guidelines and restrictions as the design entry. The altpll behavioral and timing models do not simulate jitter, lock time, or VCO drift. The behavioral models for altpll reside in the \quartus\eda\sim_lib directory. ALTERA_MF.VHD contains the VHDL behavioral models and can be used for Cyclone designs that instantiate altpll. ALTERA_MF.v contains the Verilog HDL behavioral models. The behavioral model does not perform parameter error checking, and you must specify only valid values. 1 You must set the resolution of the simulator to units of pico seconds (ps) to simulate the model successfully. A larger resolution rounds off the calculations, providing incorrect results. Altera Corporation May 2003 6-37 Preliminary Cyclone Device Handbook, Volume 1 Global Clock Network Cyclone FPGAs have eight global clock networks. The four dedicated clock input pins (CLK[3..0]), eight dual-purpose clock pins (DPCLK[7..0]), and PLL clock outputs can drive the global clock networks. In addition, internal logic for internally-generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout can drive the global clock networks. The eight global clock lines that comprise the global clock network drive throughout the entire device. You can use the global clock network as clock sources for all device resources, including IOEs, logic elements (LEs), and memory blocks. You can also use global clock resources for control signals, such as clock enables and synchronous or asynchronous clears fed from external pins. 6-38 Preliminary Altera Corporation May 2003 Global Clock Network Figure 6-18 shows the global clock network resources. Figure 6-18. Global Clock Generation DPCLK2 DPCLK3 8 (3) DPCLK1 From Core Logic Global Clock Network DPCLK4 From Core Logic CLK0 (2) CLK1 PLL1 2 4 4 2 PLL2 (1) CLK2 CLK3 (2) (3)DPCLK0 DPCLK5(3) DPCLK7 DPCLK6 Notes to Figure 6-18: (1) (2) (3) The EP1C3 device contains PLL1 only. The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins CLK1 and CLK3. The EP1C3 device in the 100-pin TQFP package has five DPCLK pins (DPCLK2, DPCLK3, DPCLK4, DPCLK6, and DPCLK7). For more information, see ""Dual-Purpose Clock I/O Pins" on page 6-40. Altera Corporation May 2003 6-39 Preliminary Cyclone Device Handbook, Volume 1 Dedicated Clock Input Pins Cyclone FPGAs have up to four dedicated clock input pins (CLK[3..0], two on the left and right side of the device. You can use the CLK[3..0] pins to drive the PLLs, or directly drive them onto the global clock network. Table 6-18 shows which clock pins drive which global clock network. Table 6-18. Dedicated Clock Input Pin Connections to Global Clock Network Clock Input Pin CLK0 CLK1 (1) CLK2 CLK3 (1) Note to Table 6-18: (1) The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins CLK1 and CLK3. GCLK0 v GCLK1 GCLK2 v GCLK3 GCLK4 GCLK5 GCLK6 GCLK7 v v v v v v Dual-Purpose Clock I/O Pins Cyclone FPGAs can have up to eight dual-purpose clock pins, DPCLK[7..0] (two on each side of the device). These dual-purpose pins can connect to the global clock network. You can use the DPCLK[7..0] pins for high fanout control signals, such as asynchronous clears, presets, clock enables, or protocol control signals (e.g., TRDY and IRDY for PCI, or DQS signals for external memory interfaces). These pins are also available as general-purpose I/O pins, meaning they can be inputs, outputs, or bidirectional pins. Table 6-19 shows which dual-purpose clock pins drive which global clock network in Cyclone FPGAs. Table 6-19. Dual-Purpose Clock I/O Connections to the Global Clock Network (Part 1 of 2) DualPurpose Clock Pin DPCLK0(1) DPCLK1(1) DPCLK2 DPCLK3 DPCLK4 GCLK0 GCLK1 GCLK2 GCLK3 v GCLK4 GCLK5 GCLK6 GCLK7 v v v v 6-40 Preliminary Altera Corporation May 2003 Global Clock Network Table 6-19. Dual-Purpose Clock I/O Connections to the Global Clock Network (Part 2 of 2) DualPurpose Clock Pin DPCLK5(1) DPCLK6 DPCLK7 Note to Table 6-19: (1) The EP1C3 device in the 100-pin TQFP package does not have the DPCLK0, DPCLK1, or DPCLK5 pins GCLK0 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7 v v v Combined Sources Table 6-20 shows which combined sources drive which global clock network. Table 6-20. Global Clock Network Sources (Part 1 of 2) Source PLL1 G0 GCLK0 GCLK1 v GCLK2 v GCLK3 GCLK4 GCLK5 GCLK6 GCLK7 PLL Counter Outputs PLL1 G1 PLL2 G0 (1) PLL2 G1 (1) CLK0 v v v v v v v v v v v v v v Dedicated CLK1 (2) Clock Input Pins CLK2 CLK3 (2) Altera Corporation May 2003 6-41 Preliminary Cyclone Device Handbook, Volume 1 Table 6-20. Global Clock Network Sources (Part 2 of 2) Source DPCLK0 DPCLK1 (3) DPCLK2 GCLK0 GCLK1 GCLK2 GCLK3 v GCLK4 GCLK5 GCLK6 GCLK7 v v v v v v v DualDPCLK3 Purpose Clock Pins DPCLK4 DPCLK5 DPCLK6 DPCLK7 Notes to Table 6-20: (1) (2) (3) The EP1C3 device only has PLL1. The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins CLK1 and CLK3. The EP1C3 device does not have DPCLK1. In the Cyclone FPGA, there are eight distinct dedicated global clock networks. Multiplexers are used with these clocks to form six-bit buses to drive LAB row clocks, column IOE clocks, or row IOE clocks (see Figure 6-19). Another multiplexer is used at the LAB level to select two of the six row clocks to feed the LE registers within the LAB. Figure 6-19. Global Clock Network Multiplexers Global Clock Network 4 Dedicated Clock Inputs [3..0] 8 Dual-Purpose Clock I/Os [7..0] 4 PLL Outputs [3..0] Core Logic [7..0] 8 6 Row I/O Region IO_CLK[5..0] Clock [7..0] 8 6 Lab Row Clock [5..0] 6 Column I/O Region IO_CLK[5..0] IOE clocks have horizontal (row) and vertical (column) block regions that are clocked by six I/O clock signals chosen from the eight global clock resources. Figure 6-20 shows the I/O clock regions. 6-42 Preliminary Altera Corporation May 2003 Conclusion Figure 6-20. I/O Clock Regions Vertical I/O Region IO_CLK[5..0] 6 I/O Clock Regions 6 LAB Row Clocks IO_CLK[5..0] LAB Row Clocks IO_CLK[5..0] 6 6 LAB Row Clocks IO_CLK[5..0] LAB Row Clocks IO_CLK[5..0] 6 6 LAB Row Clocks IO_CLK[5..0] 8 Global Clock Network LAB Row Clocks IO_CLK[5..0] 6 Horizontal I/O Regions 6 LAB Row Clocks IO_CLK[5..0] LAB Row Clocks IO_CLK[5..0] 6 6 LAB Row Clocks IO_CLK[5..0] LAB Row Clocks IO_CLK[5..0] 6 6 Vertical I/O Region IO_CLK[5..0] Conclusion Cyclone PLLs provide significant features such as M/(N x post-scale) multiplication/division, phase shift, and programmable duty cycle for your cost-sensitive clock synthesis applications. The reduction in clock delay, and the elimination of clock skew within the device, improves design speed. Cyclone PLL features simplify board design by running the internal logic of the device at a faster rate than the input clock frequency. Altera Corporation May 2003 6-43 Preliminary Cyclone Device Handbook, Volume 1 6-44 Preliminary Altera Corporation May 2003 Section III. Memory This section provides information on the M4K embedded memory blocks internal to Cyclone devices. It contains the following: Chapter 7. On-Chip Memory Implementations Using Cyclone Memory Blocks Revision History The table below shows the revision history for Chapter 7. Chapter(s) 7 Date / Version May 2003 v1.0 Changes Made Updated Table 7-2 with EP1C4. Altera Corporation Part III-1 Preliminary Memory Cyclone Device Handbook, Volume 1 Part III-2 Preliminary Altera Corporation 7. On-Chip Memory Implementations Using Cyclone Memory Blocks C51007-1.0 Introduction CycloneTM devices feature embedded memory blocks that can be easily configured to support a wide range of system requirements. These M4K memory blocks present a very flexible and fast memory solution that you can use to provide excellent memory bandwidth and density for a host of cost-sensitive applications. You can use M4K memory blocks in various memory modes, including single-port, simple dual-port, true dual-port (also known as bidirectional dual-port), shift-register, ROM, and first-in first-out (FIFO) mode. M4K memory blocks also include advanced features such as support for byte-enable operation, parity-bit-based error correction, and mixed-port widths. This application note describes these modes and other characteristics of the M4K memory blocks. M4K Memory Features Table 7-1 summarizes the features supported by the M4K memory block. Table 7-1. Summary of M4K Memory Features (Part 1 of 2) Performance Total RAM bits (including parity bits) Configurations 200 MHz 4,608 4K x 1 2K x 2 1K x 4 512 x 8 512 x 9 256 x 16 256 x 18 128 x 32 128 x 36 (1) Parity bits Byte enable Single-port memory Simple dual-port memory True dual-port memory Embedded shift register ROM v v v v v v v Altera Corporation May 2003 7-1 Preliminary Cyclone Device Handbook, Volume 1 Table 7-1. Summary of M4K Memory Features (Part 2 of 2) FIFO buffer Simple dual-port mixed width support True dual-port mixed width support Memory initialization (.mif) Mixed-clock mode Power-up condition Register clears Same-port read-during-write Mixed-port read-during-write Notes to Table 7-1: (1) (2) The Altera(R) Quartus(R) II software will automatically cascade or concatenate multiple M4K memory blocks to provide deeper or wider memory functions. Asserting the clear port of the rden and byte-enable registers drives the output of these registers high. v v v v v Outputs cleared Input and output registers (2) New data available at positive clock edge Outputs set to unknown or old data Table 7-2 shows the memory capacity for M4K memory blocks in each Cyclone device. Table 7-2. M4K Memory Distribution in Cyclone Devices Device EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 1 1 1 2 2 Columns 13 17 20 52 64 Blocks Total RAM Bits 59,904 78,336 92,160 239,616 294,912 Parity Bit Support M4K memory blocks support an optional parity bit for each data byte. Of the 4,608 bits of storage space available in an M4K block, 512 are available for use as parity-bit storage. The parity bit, along with logic implemented in logic elements (LEs), can facilitate parity-checking methods of error detection to ensure data integrity. You can also use parity-size data words to store user-specified control bits or as extra data bits to provide support for 9-bit, 18-bit, or 36-bit wide memories. 7-2 Preliminary Altera Corporation May 2003 M4K Memory Features Byte-Enable Support Byte-enable signals can be used to mask the input data so that only specific bytes in memory are overwritten. The unwritten bytes retain the data value that was last written to them. The write-enable signal (wren) is used in conjunction with byte-enable signals (byteena) to control the M4K block's write operations. The default value for the byteena signal is high (enabled), in which case no bytes are masked and writing is controlled only by the wren signals. Asserting the clear port of the byte-enable register drives the byte-enable signal to its default high level. M4K blocks support byte write operations when the write port has a data width of 16, 18, 32, or 36 bits. Table 7-3 summarizes how byteena controls which bits are masked. Table 7-3. Byte Enable for M4K Blocks byteena [0] = 1 [1] = 1 [2] = 1 [3] = 1 Notes to Table 7-3: (1) (2) Note (1), (2) datain x 36 [8..0] [17..9] [26..18] [35..27] datain x 18 [8..0] [17..9] - Any combination of byte-enable signals is possible. Byte enables can be used in the same manner with 8-bit words, i.e., in x 32 modes. x 16 and Figure 7-1 shows how both the wren and the byteena signals control the write operations of the RAM. Altera Corporation May 2003 7-3 Preliminary Cyclone Device Handbook, Volume 1 Figure 7-1. Byte-Enable Operation Functional Waveform inclock wren an a0 a1 a2 a0 a1 a2 address data_in XXXX ABCD XXXX byteena XX 10 01 11 XX contents at a0 FFFF ABFF contents at a1 FFFF FFCD contents at a2 FFFF ABCD asynch_data_out doutn ABXX XXCD ABCD ABFF FFCD ABCD Power-up Conditions & Memory Initialization Upon power-up, M4K memory is in an idle state. The outputs always power-up to zero, regardless of whether the output registers are used or bypassed. Even if a memory initialization file is used to pre-load the contents of the RAM block, the outputs will still power-up cleared. For example, if address 0 is pre-initialized to FF, the M4K blocks power-up with the output at 00. Using M4K Memory f M4K memory blocks include input registers that synchronize write operations and output registers to pipeline designs and improve system performance. All M4K memory blocks are fully synchronous, meaning that all inputs are registered, but outputs can be either registered or combinatorial. M4K memory can emulate asynchronous memory. For more information, see Application Note 210: Converting Memory from Asynchronous to Synchronous for Stratix Designs. 7-4 Preliminary Altera Corporation May 2003 Using M4K Memory M4K memory blocks can operate in various modes, including: Single-port Simple dual-port True dual-port (bidirectional dual-port) Shift-register ROM FIFO Implementing Single-Port Mode Single-port mode supports non-simultaneous read and write operations. Figure 7-2 shows the single-port memory configuration for M4K blocks. Figure 7-2. Single-Port Memory data[ ] address[ ] wren inclock inclocken inaclr Note (1) q[ ] outclock outclocken outaclr Note to Figure 7-2: (1) Two single-port memory blocks can be implemented in a single M4K block. M4K memory blocks can also be divided in half and used for two independent single-port RAM blocks. The Quartus II software automatically uses this method of single-port memory packing when running low on memory resources. When deliberately assigning two single-port memories to one M4K block, first ensure that each of the two independent RAM blocks is equal to or less than half the size of the M4K block. In the single-port RAM configuration, the outputs can only be in readduring-write mode, which means that during the write operation, data written to the RAM flows through to the RAM outputs. When the output registers are bypassed, the new data is available on the rising edge of the same clock cycle on which it was written. f For more information about read-during-write mode, see "Read-duringWrite Operation at the Same Address" on page 7-20. Figure 7-3 shows timing waveforms for read and write operations in single-port mode. Altera Corporation May 2003 7-5 Preliminary Cyclone Device Handbook, Volume 1 Figure 7-3. Single-Port Timing Waveforms in clock wren an-1 an a0 a1 a2 a3 a4 a5 a6 address data_in din-1 din din4 din5 din6 synch_data_out din-2 din-1 din dout0 dout1 dout2 dout3 din4 asynch_data_out din-1 din dout0 dout1 dout2 dout3 din4 din5 Implementing Simple Dual-Port Mode Simple dual-port memory supports simultaneous read and write operations. Figure 7-4 shows the simple dual-port memory configuration for M4K blocks. Figure 7-4. Simple Dual-Port Memory data[ ] wraddress[ ] wren inclock inclocken inaclr Note (1) rdaddress[ ] rden q[ ] outclock outclocken outaclr Note to Figure 7-4: (1) Simple dual-port RAM supports read/write clock mode in addition to the input/output clock mode shown. M4K memory supports mixed-width configurations, allowing different read and write port widths. This capability is useful for many applications, including implementing serializer-deserializers (SERDES) 7-6 Preliminary Altera Corporation May 2003 Using M4K Memory as well as interfacing with buses of differing widths. Table 7-4 shows the mixed-width configurations supported by the M4K blocks in Cyclone devices.. Table 7-4. M4K Block Mixed-Width Configurations (Simple Dual-Port Mode) Read Port 4K x 1 2K x 2 1K x 4 512 x 8 256 x 16 128 x 32 512 x 9 256 x 18 128 x 36 Write Port 4K x 1 v v v v v v 2K x 2 v v v v v v 1K x 4 v v v v v v 512 x 8 v v v v v v 256 x 16 128 x 32 v v v v v v v v v v v v v v v v v v v v v 512 x 9 256 x 18 128 x 36 In simple dual-port mode, M4K blocks have one write-enable and one read-enable signal. On the M4K block, asserting the clear port of the rden register drives rden high, which allows the read operation to occur. When the read-enable signal is deactivated, the current data is retained at the output ports. If the read-enable signal is activated during a write operation with the same address location selected, the simple dual-port RAM output is either unknown or can be set to output the old data stored at the memory address. f For more information, see "Read-during-Write Operation at the Same Address" on page 7-20. Figure 7-5 shows timing waveforms for read and write operations in simple dual-port mode. Altera Corporation May 2003 7-7 Preliminary Cyclone Device Handbook, Volume 1 Figure 7-5. Simple Dual-Port Timing Waveforms wrclock wren wraddress an-1 an a0 a1 a2 a3 a4 a5 a6 data_in din-1 din din4 din5 din6 rdclock rden rdaddress bn b0 b1 b2 b3 synch_data_out doutn-2 doutn-1 doutn asynch_data_out doutn-1 doutn dout0 Implementing True Dual-Port Mode M4K blocks offer a true dual-port mode to support any combination of two-port operations: two read operations, two write operations, or one read operation and one write operation at two different clock frequencies. True dual-port memory can be used to increase memory bandwidth in numerous applications. An example system that benefits from the use of true dual-port memory is a system containing an Altera Nios(R) embedded processor and a direct memory access (DMA) controller. Such a system will experience bottlenecks if the processor and the DMA controller need simultaneous access to single-port memory. The ability of both the processor and the DMA controller to access the M4K memory simultaneously, avoiding the need for arbitration, can dramatically improve bandwidth in this type of system. Figure 7-6 shows the true dual-port memory configuration for M4K blocks. 7-8 Preliminary Altera Corporation May 2003 Using M4K Memory Figure 7-6. True Dual-Port Memory A dataA[ ] addressA[ ] wrenA clockA clockenA qA[ ] aclrA Note (1) B dataB[ ] addressB[ ] wrenB clockB clockenB qB[ ] aclrB Note to Figure 7-6: (1) True dual-port memory supports input/output clock mode in addition to the independent clock mode shown. The widest bit configuration of a single M4K block in true dual-port mode is 256 x 16-bit (or 256 x 18-bit with parity). The 128 x 32-bit (128 x 36-bit with parity) configuration of the M4K block is unavailable because the number of output drivers is equivalent to the maximum bit width of the M4K block. Because true dual-port RAM has outputs on two ports, the maximum width of the true dual-port RAM equals half of the total number of output drivers. However, multiple M4K blocks can be concatenated to support wider memory configurations. Table 7-5 lists the possible M4K RAM block configurations. Table 7-5. M4K Block Mixed-Port Width Configurations (True Dual-Port Mode) Port B Port A 4K x 1 2K x 2 4K x 1 2K x 2 1K x 4 512 x 8 256 x 16 512 x 9 256 x 18 v v v v v v v v v v 1K x 4 v v v v v 512 x 8 256 x 16 512 x 9 256 x 18 v v v v v v v v v v v v v v Altera Corporation May 2003 7-9 Preliminary Cyclone Device Handbook, Volume 1 In true dual-port mode, the RAM outputs can only be configured for read-during-write mode. This means that during write operation, data being written to the A or B port of the RAM flows through to the A or B outputs, respectively. When the output registers are bypassed, the new data is available on the rising edge of the same clock cycle it was written on. f For sample waveforms and other information on mixed-port readduring-write mode, see "Read-during-Write Operation at the Same Address" on page 7-20. Potential write conflicts must be resolved external to the RAM because simultaneously writing to the same address location at both ports results in unknown data storage at that location. For a valid write operation to the same address of the RAM block, the rising edge of the write clock for port A must occur following the minimum write cycle time interval after the rising edge of the write clock for port B. Since data is written into the M4K blocks at the falling edge of the write clock, the rising edge of the write clock for port A should occur following half of the minimum write cycle time interval after the falling edge of the write clock for port B. If this timing is not met, the data stored in that particular address will be invalid. f See Section I, Cyclone FPGA Family Data Sheet for more information about the minimum synchronous write cycle time. Figure 7-7 shows true dual-port timing waveforms for a write operation at port A and a read operation at port B. 7-10 Preliminary Altera Corporation May 2003 Using M4K Memory Figure 7-7. True Dual-Port Timing Waveforms A_clk A_wren A_address an-1 an a0 a1 a2 a3 a4 a5 a6 A_data_in din-1 din din4 din5 din6 A_synch_data_out din-2 din-1 din dout0 dout1 dout2 dout3 din4 A_asynch_data_out din-1 din dout0 dout1 dout2 dout3 din4 din5 B_clk B_wren B_address bn b0 b1 b2 b3 B_synch_data_out doutn-2 doutn-1 doutn dout0 dout1 B_asynch_data_out doutn-1 doutn dout0 dout1 dout2 Implementing Shift-Register Mode Embedded memory configurations can implement shift-register blocks for digital signal processing (DSP) applications, such as finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, and auto-correlation and cross-correlation functions. These and other DSP applications require local data storage, traditionally implemented with standard flip-flops that can quickly consume many logic cells for large shift registers. A more efficient alternative is to use embedded memory as a shift-register block, which saves logic cell and routing resources and provides a more efficient implementation. The size of a (w x m x n) shift register is determined by the input data width (w), the length of the taps (m), and the number of taps (n). The size of a (w x m x n) shift register must be less than or equal to the 4,608 bits. In addition, the size of (w x n) must be less than or equal to 36 bits. If a larger shift register is required, memory blocks can be cascaded together. Data is written into each address location at the falling edge of the clock and read from the address at the rising edge of the clock. The shiftregister mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. Figure 7-8 shows the M4K memory block in shift-register mode. Altera Corporation May 2003 7-11 Preliminary Cyclone Device Handbook, Volume 1 Figure 7-8. M4K Shift-Register Memory Configuration w x m x n Shift Register m-Bit Shift Register w w m-Bit Shift Register w w n Number of Taps m-Bit Shift Register w w m-Bit Shift Register w w Implementing ROM Mode M4K blocks can also be configured as ROM. ROM can be initialized in an M4K block by using a memory initialization file (.mif). Because all M4K memory configurations must have synchronous inputs, the address lines of the ROM are registered. ROM outputs can be registered or combinatorial. The read operation of the ROM is identical to the read operation of the single-port RAM configuration. Implementing FIFO Buffers FIFO buffer outputs are always combinatorial. Simultaneous read and write operations from an empty FIFO buffer are not supported. 7-12 Preliminary Altera Corporation May 2003 Clock Modes Clock Modes Depending on the M4K memory mode, independent, input/output, read/write, and/or single-port clock modes are available. Table 7-6 shows the clock modes supported by the M4K memory modes. Table 7-6. M4K Memory Clock Modes Clocking Mode Independent Input/output Read/write Single-port True-Dual Port Mode v v Simple DualPort Mode Single-Port Mode v v v Independent Clock Mode M4K memory blocks can implement independent clock mode for true dual-port memory. In this mode, a separate clock is available for each port (A and B). Clock A controls all registers on the port A side, while clock B controls all registers on the port B side. Each port also supports independent clock-enable signals and asynchronous clear signals for port A and B registers. Figure 7-9 shows an M4K memory block in independent clock mode. Altera Corporation May 2003 7-13 Preliminary 7-14 Preliminary 8 LAB Row Clocks A D ENA ENA Q B 8 Data In Q D 8 Data In Figure 7-9. Independent Clock Mode Cyclone Device Handbook, Volume 1 dataA[ ] Memory Block 256 16 (2) 512 8 1,024 4 2,048 2 4,096 1 dataB[ ] byteenaA[ ] D ENA Q Byte Enable A Byte Enable B Q D ENA byteenaB[ ] addressA[ ] D ENA Q Address A Address B Q D ENA addressB[ ] wrenA wrenB clkenA ENA D Q clockA Data Out Write Pulse Generator Write/Read Enable Write/Read Enable Q D ENA Write Pulse Generator Data Out clkenB clockB D ENA Q Q D ENA qA[ ] qB[ ] Altera Corporation May 2003 Clock Modes Input/Output Clock Mode M4K memory blocks can implement input/output clock mode for true and simple dual-port memory. On each of the two ports, A and B, one clock controls all registers for inputs (data input, wren, and address) into the memory block. The other clock controls the block's data output registers. Each memory block port also supports independent clock enables and asynchronous clear signals for input and output registers. Figures 7-10 and 7-11 show the memory block in input/output clock mode for true and simple dual-port modes, respectively. Altera Corporation May 2003 7-15 Preliminary 7-16 Preliminary 8 LAB Row Clocks 8 Q ENA D 8 A D ENA Q B Data In Cyclone Device Handbook, Volume 1 dataA[ ] Data In Memory Block 256 x 16 (2) 512 x 8 1,024 x 4 2,048 x 2 4,096 x 1 Byte Enable B Q ENA D dataB[ ] byteenaA[ ] D ENA Q Byte Enable A byteenaB[ ] addressA[ ] D ENA Q Address A Address B Q D ENA addressB[ ] wrenA wrenB D ENA Q Figure 7-10. Input/Output Clock Mode in True Dual-Port Mode clkenA clockA Data Out Write Pulse Generator Data Out Write/Read Enable Write/Read Enable Q D ENA Write Pulse Generator clkenB D ENA Q Q D ENA clockB qA[ ] qB[ ] Altera Corporation May 2003 Clock Modes Figure 7-11. Input/Output Clock Mode in Simple Dual-Port Mode 8 LAB Row Clocks 8 data[ ] D Q ENA Note (1) Data In Memory Block 256 16 512 8 1,024 4 2,048 2 4,096 1 address[ ] D Q ENA Read Address Data Out byteena[ ] D Q ENA Byte Enable D Q ENA To MultiTrack Interconnect wraddress[ ] D Q ENA Write Address rden D Q ENA wren Read Enable outclken inclken wrclock D Q ENA Write Pulse Generator Write Enable rdclock Note to Figure 7-11: (1) For more information on the MultiTrackTM interconnect, see Section I, Cyclone FPGA Family Data Sheet. Read/Write Clock Mode M4K memory blocks can implement read/write clock mode for simple dual-port memory. This mode can use up to two clocks. The write clock controls the block's data inputs, wraddress, and wren. The read clock controls the data output, rdaddress, and rden. The memory blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. Figure 7-12 shows a memory block in read/write clock mode. Altera Corporation May 2003 7-17 Preliminary Cyclone Device Handbook, Volume 1 Figure 7-12. Read/Write Clock Mode in Simple Dual-Port Mode 8 LAB Row Clocks 8 data[ ] D Q ENA Note (1) Memory Block 256 x 16 512 x 8 1,024 x 4 Data In 2,048 x 2 4,096 x 1 Data Out D Q ENA To MultiTrack Interconnect address[ ] D Q ENA Read Address wraddress[ ] D Q ENA Write Address byteena[ ] D Q ENA Byte Enable rden D Q ENA wren Read Enable outclken inclken wrclock D Q ENA Write Pulse Generator Write Enable rdclock Note to Figure 7-12: (1) For more information on the MultiTrack interconnect, see Section I, Cyclone FPGA Family Data Sheet. Single-Port Mode The M4K memory blocks can implement single-port clock mode when simultaneous read and write operations are not required (see Figure 7-13). A single block in a memory block can support up to two single-port mode RAM blocks in M4K blocks. 7-18 Preliminary Altera Corporation May 2003 Synchronous & Pseudo-Asynchronous Modes Figure 7-13. Single-Port Mode 8 LAB Row Clocks Note (1) 8 data[ ] D Q ENA RAM/ROM 256 x 16 512 x 8 1,024 x 4 Data In 2,048 x 2 4,096 x 1 Data Out D Q ENA To MultiTrack Interconnect address[ ] D Q ENA Address wren Write Enable outclken inclken inclock D Q ENA Write Pulse Generator outclock Note to Figure 13: (1) For more information on the MultiTrack interconnect, see Section I, Cyclone FPGA Family Data Sheet. Synchronous & PseudoAsynchronous Modes The M4K memory architecture implements synchronous, pipelined RAM by registering both the input and output signals to the RAM block. All M4K memory inputs are registered, providing synchronous write cycles. In synchronous operation, an M4K block generates its own self-timed strobe write enable (wren) signal derived from the global or regional clock. In contrast, a circuit using asynchronous RAM must generate the RAM wren signal while ensuring its data and address signals meet setup and hold time specifications relative to the wren signal. The output registers can be bypassed. In an asynchronous memory, neither the input nor the output is registered. While Cyclone devices do not support asynchronous memory, they do support a pseudo-asynchronous read operation where the output data is available during the same clock cycle as when the read address is driven into it. Pseudo-asynchronous reading is possible in the simple and Altera Corporation May 2003 7-19 Preliminary Cyclone Device Handbook, Volume 1 true dual-port modes of the M4K blocks by clocking the read enable and read address registers on the negative clock edge and bypassing the output registers. f For more information, see AN 210: Converting Memory from Asynchronous to Synchronous for Stratix Designs. The following two sections describe the functionality of the various M4K memory configurations when reading from an address during a write operation at that same address. There are two types of read-during-write operations: same-port and mixed-port. Figure 7-14 illustrates the difference in data flow between same-port and mixed-port read-duringwrite. Figure 7-14. Read-during-Write Data Flow Port A data in Port B data in Mixed-port data flow Same-port data flow Port A data out Port B data out Read-duringWrite Operation at the Same Address Same-Port Read-during-Write Mode For read-during-write operation of a single-port RAM or the same port of a true dual-port RAM, the new data is available on the rising edge of the same clock cycle it was written on. See Figure 7-15 for a sample functional waveform. When using byte-enable signals in true dual-port RAM mode, the outputs for the masked bytes on the same port are unknown. (See Figure 7-1.) The non-masked bytes are read out as shown in Figure 7-15. 7-20 Preliminary Altera Corporation May 2003 Read-during-Write Operation at the Same Address Figure 7-15. Same-Port Read-during-Write Functionality Note (1) inclock data_in A B wren data_out Old A Note to Figure 7-15: (1) Outputs are not registered. Mixed-Port Read-during-Write Mode This mode is used when a RAM in simple or true dual-port mode has one port reading and the other port writing to the same address location with the same clock. You can configure the M4K memory block to operate in this mode and modify the parameter shown below using the MegaWizard(R) Plug-In Manager included with the Quartus II software. The READ_DURING_WRITE_MODE_MIXED_PORTS parameter for M4K memory blocks determines whether or not to output the old data at the address. Setting this parameter to OLD_DATA outputs the old data at that address. Setting this parameter to DONT_CARE outputs an unknown value. During the instantiation of an ALTSYNCRAM or LPM_RAM_DP+ storage megafunction using the Quartus II software, the MegaWizard plug-in manager asks "How should the q output behave when reading a memory location that is being written from the other port?" Clicking "I don't care" assigns the DONT_CARE value to the parameter, and clicking "Old memory contents appear" assigns the OLD_DATA value to the parameter. 1 Altera recommends using the MegaWizard Plug-In Manager to create these memory megafunctions rather than directly creating instances. Once a storage megafunction is created using the MegaWizard Plug-In Manager, use the MegaWizard Plug-In Manager to make any necessary changes. See Figures 7-16 and 7-17 for sample functional waveforms showing mixed-port read-during-write mode operation. These figures assume that the outputs are not registered. Altera Corporation May 2003 7-21 Preliminary Cyclone Device Handbook, Volume 1 Figure 7-16. Mixed-Port Read-during-Write: OLD_DATA inclock addressA and addressB Port A data_in Port A wren Port B wren Port B data_out Old A B A Address Q B Figure 7-17. Mixed-Port Read-during-Write: DONT_CARE inclock addressA and addressB Port A data_in Port A wren Port B wren Port B data_out Unknown B A Address Q B When two different clocks are used in dual-port RAM, the read-duringwrite behavior depends on the relationship of the clocks. The writing of the new contents starts at the falling edge of the write clock. Therefore, if the read clock's rising edge occurs before the falling edge of the write clock, the old data is read out. If the read clock's rising edge occurs between the falling edge of the write clock and half the minimum write cycle time interval, the output is unknown data. f For the minimum synchronous-write-cycle time see Section I, Cyclone FPGA Family Data Sheet. 7-22 Preliminary Altera Corporation May 2003 Conclusion Conclusion M4K memory blocks are a flexible memory solution available in Cyclone devices that provide advanced features such as byte-enable capability, parity bit storage capability, and shift-register mode, as well as mixedport width support and true dual-port mode. This flexibility makes these embedded memory blocks well suited for a wide range of applications including ATM cell packet processing, header/cell storage, channelized functions, and program memory for processors. Altera Corporation May 2003 7-23 Preliminary Cyclone Device Handbook, Volume 1 7-24 Preliminary Altera Corporation May 2003 Section IV. I/O Standards This section provides information on the Cyclone FPGA I/O capabilities. It also includes information on selecting I/O standards for Cyclone devices in the Quartus II software. This section contains the following chapters: Chapter 8. Using Selectable I/O Standards in Cyclone Devices Chapter 9. Implementing LVDS in Cyclone Devices Revision History The table below shows the revision history for Chapter 8 and 9. Chapter(s) 8 Date / Version May 2003 v1.0 Changes Made Added Figure 8-5 and section titled "Differential SSTL-2 - EIA/JEDEC Standard JESD8-9A". Added last row to Table 8-1 for Differential SSTL - 2. 9 May 2003 v1.0 Revised Table 9-1 with EP1C4. Altera Corporation Section IV-1 Preliminary I/O Standards Cyclone Device Handbook, Volume 1 Section IV-2 Preliminary Altera Corporation 8. Using Selectable I/O Standards in Cyclone Devices C51008-1.0 Introduction The proliferation of I/O standards and the need for improved I/O performance have made it critical that low-cost devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-2, SSTL-3, and LVDS compatibility allow CycloneTM devices to connect to other devices on the same printed circuit board (PCB) that may require different operating and I/O voltages. With these aspects of implementation easily manipulated using the Altera(R) Quartus(R) II software, the Cyclone device family enables system designers to use low-cost FPGAs while keeping pace with increasing design complexity. This application note is a guide to understanding the input/output capabilities of the Cyclone devices, including: Supported I/O Standards Cyclone I/O Banks Programmable Current Drive Strength Hot Socketing I/O Termination Pad Placement & DC Guidelines Quartus II Software Support "Quartus II Software Support" on page 8-17 describes how to use the Quartus II software to specify device and pin options and assign pins to implement the above features of Cyclone devices. Altera Corporation May 2003 8-1 Preliminary Cyclone Device Handbook, Volume 1 Supported I/O Standards f Cyclone devices support the I/O standards shown in Table 8-1. See Section I, Cyclone FPGA Family Data Sheet for more details on the I/O Standards discussed in this section. Table 8-1. I/O Standards Supported by Cyclone Devices I/O Standard 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS PCI SSTL-3 Class I and II SSTL-2 Class I and II LVDS Compatibility Differential SSTL - 2 Notes to Table 8-1: (1) (2) (3) Notes (1), (2) Output Voltage Level (V) 3.3 2.5 1.8 1.5 3.3 3.3 2.5 VOD = 0.25 to 0.55 2.5 Type Single-ended Single-ended Single-ended Single-ended Single-ended Voltage-referenced Voltage-referenced Differential Differential Input Voltage Level (V) 3.3/2.5 3.3/2.5 3.3/2.5/1.8 3.3/2.5/1.8/1.5 3.3 -0.3 to 3.9 -0.3 to 3.0 0 to 2.4 N/A (3) Input VREF (V) N/A N/A N/A N/A N/A 1.5 1.25 N/A 1.25 Output VCCIO (V) 3.3 2.5 1.8 1.5 3.3 3.3 2.5 2.5 2.5 Termination VTT (V) N/A N/A N/A N/A N/A 1.5 1.25 N/A 1.25 The EP1C3 device in the 100-pin thin quad flat pack (TQFP) package does not have support for a PLL LVDS input or an external clock output. Cyclone devices have dual-purpose differential inputs. Outputs are balanced SSTL outputs requiring an external resistor divider. This I/O standard is only available on output clock pins (PLL_OUT pins). 3.3-V LVTTL (EIA/JEDEC Standard JESD8-B) The 3.3-V LVTTL I/O standard is a general-purpose, single-ended standard used for 3.3-V applications. The LVTTL standard defines the DC interface parameters for digital circuits operating from a 3.0-V/3.3-V power supply and driving or being driven by LVTTL-compatible devices. 8-2 Preliminary Altera Corporation May 2003 Supported I/O Standards The LVTTL input standard specifies a wider input voltage range of - 0.3 V VI 3.9 V. Altera recommends an input voltage range of - 0.5 V VI 4.1 V. The LVTTL standard does not require input reference voltages or board terminations. Cyclone devices support both input and output levels for 3.3-V LVTTL. 3.3-V LVCMOS (EIA/JEDEC Standard JESD8-B) The 3.3-V LVCMOS I/O standard is a general-purpose, single-ended standard used for 3.3-V applications. The LVCMOS standard defines the DC interface parameters for digital circuits operating from a 3.0-V or 3.3-V power supply and driving or being driven by LVCMOS-compatible devices. The LVCMOS standard specifies the same input voltage requirements as LVTTL (- 0.3 V VI 3.9 V). The output buffer drives to the rail to meet the minimum high-level output voltage requirements. The 3.3-V I/O Standard does not require input reference voltages or board terminations. Cyclone devices support both input and output levels specified by the 3.3-V LVCMOS I/O standard. 2.5-V LVTTL Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-5) The 2.5-V I/O standard is used for 2.5-V LVTTL applications. This standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other 2.5-V devices. The input and output voltage requirements are: The 2.5-V normal and wide range input standards specify an input voltage range of - 0.3 V VI 3.0-V. The normal range minimum high-level output voltage requirement (VOH) is 2.1-V. The wide range minimum high-level output voltage requirement (VOH) is VCCIO - 0.2-V. The 2.5-V standard does not require input reference voltages or board terminations. Cyclone devices support input and output levels for both 2.5-V LVTTL ranges. Altera Corporation May 2003 8-3 Preliminary Cyclone Device Handbook, Volume 1 2.5-V LVCMOS Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-5) The 2.5-V I/O standard is used for 2.5-V LVCMOS applications. This standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other 2.5-V parts. The input and output voltage ranges are: The 2.5-V normal and wide range input standards specify an input voltage range of - 0.3-V VI 3.0-V. The normal range minimum VOH requirement is 2.1-V. The wide range minimum VOH requirement is VCCIO - 0.2 V. The 2.5-V standard does not require input reference voltages or board terminations. Cyclone devices support input and output levels for both 2.5-V LVCMOS ranges. 1.8-V LVTTL Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-7) The 1.8-V I/O standard is used for 1.8-V LVTTL applications. This standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other 1.8-V parts. The input and output voltage ranges are: The 1.8-V normal and wide range input standards specify an input voltage range of - 0.3 V VI 2.25 V. The normal range minimum VOH requirement is VCCIO - 0.45 V. The wide range minimum VOH requirement is VCCIO - 0.2 V. The 1.8-V standard does not require input reference voltages or board terminations. Cyclone devices support input and output levels for both normal and wide 1.8-V LVTTL ranges. 1.8-V LVCMOS Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-7) The 1.8-V I/O standard is used for 1.8-V LVCMOS applications. This standard defines the DC interface parameters for high-speed, lowvoltage, non-terminated digital circuits driving or being driven by other 1.8-V devices. The input and output voltage ranges are: The 1.8-V normal and wide range input standards specify an input voltage range of - 0.3 V VI 2.25 V. The normal range minimum VOH requirement is VCCIO - 0.45 V. The wide range minimum VOH requirement is VCCIO - 0.2 V. 8-4 Preliminary Altera Corporation May 2003 Supported I/O Standards The 1.8-V standard does not require input reference voltages or board terminations. Cyclone devices support input and output levels for both normal and wide 1.8V LVCMOS ranges. 1.5-V LVCMOS Normal & Wide Voltage Ranges (EIA/JEDEC Standard JESD8-11) The 1.5-V I/O standard is used for 1.5-V applications. This standard defines the DC interface parameters for high-speed, low-voltage, nonterminated digital circuits driving or being driven by other 1.5-V devices. The input and output voltage ranges are: The 1.5-V normal and wide range input standards specify an input voltage range of - 0.3 V VI 1.9-V. The normal range minimum VOH requirement is 1.05-V. The wide range minimum VOH requirement is VCCIO - 0.2-V. The 1.5-V standard does not require input reference voltages or board terminations. Cyclone devices support input and output levels for both normal and wide 1.5-V LVCMOS ranges. 3.3-V (PCI Special Interest Group (SIG) PCI Local Bus Specification Revision 2.2) The PCI local bus specification is used for applications that interface to the PCI local bus, which provides a processor-independent data path between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory systems. The conventional PCI specification revision 2.2 defines the PCI hardware environment including the protocol, electrical, mechanical, and configuration specifications for the PCI devices and expansion boards. This standard requires 3.3-V VCCIO. The 3.3-V PCI standard does not require input reference voltages or board terminations. Although PCI is not supported on the smallest member of the Cyclone device family, the EP1C3, all other Cyclone devices are fully compliant with the 3.3-V PCI Local Bus Specification Revision 2.2 and meet 32-bit/66-MHz operating frequency and timing requirements. The devices support PCI input and output levels on I/O banks 1 and 3 only. See "Cyclone I/O Banks" for more details. SSTL-3 Class I & II (EIA/JEDEC Standard JESD8-8) The SSTL-3 I/O standard is a 3.3-V memory bus standard used for applications such as high-speed SDRAM interfaces. This standard defines the input and output specifications for devices that operate in the Altera Corporation May 2003 8-5 Preliminary Cyclone Device Handbook, Volume 1 SSTL-3 logic switching range of 0.0 to 3.3 V. The SSTL-3 standard specifies an input voltage range of - 0.3 V VI VCCIO + 0.3-V. SSTL-3 requires a 1.5-V VREF and a 1.5-V VTT to which the series and termination resistors are connected (see Figures 8-1 and 8-2). In typical applications, both the termination voltage and reference voltage track the output supply voltage. Figure 8-1. SSTL-3 Class I Termination VTT = 1.5 V Output Buffer 25 Z = 50 VREF = 1.5 V 50 Input Buffer Figure 8-2. SSTL-3 Class II Termination VTT = 1.5 V V = = 1.5 VTTTT 1.5 V V 50 50 Output Buffer Output Buffer 2525 50 Z = 50 Z = 50 VREF = V VREF = 1.51.5 V Input Buffer Input Buffer Cyclone devices support both input and output SSTL-3 Class I & II levels. SSTL-2 Class I & II (EIA/JEDEC Standard JESD8-9A) The SSTL-2 I/O standard is a 2.5-V memory bus standard used for applications such as high-speed double data rate (DDR) SDRAM interfaces. This standard defines the input and output specifications for devices that operate in the SSTL-2 logic switching range of 0.0-V to 2.5-V. This standard improves operation in conditions where a bus must be isolated from large stubs. The SSTL-2 standard specifies an input voltage range of -0.3 V VI VCCIO + 0.3 V. SSTL-2 requires a VREF value of 1.25 V and a VTT value of 1.25 V connected to the series and termination resistors (see Figures 8-3 and 8-4). 8-6 Preliminary Altera Corporation May 2003 Supported I/O Standards Figure 8-3. SSTL-2 Class I Termination VTT = 1.25 V Output Buffer 25 Z = 50 VREF = 1.25 V 50 Input Buffer Figure 8-4. SSTL-2 Class II Termination VTT = 1.25 V VTT = 1.25 V 50 Output Buffer 25 50 Z = 50 VREF = 1.25 V Input Buffer Cyclone devices support both input and output SSTL-2 Class I & II levels. LVDS (ANSI/TIA/EIA Standard ANSI/TIA/EIA-644) The LVDS I/O standard is a differential high-speed, low-voltage swing, low-power, general-purpose I/O interface standard. This standard is used in applications requiring high-bandwidth data transfer, backplane drivers, and clock distribution. The ANSI/TIA/EIA-644 standard specifies LVDS transmitters and receivers capable of operating at recommended maximum data signaling rates of 655 Mbps. Devices can operate at slower speeds if needed however, and there is a theoretical maximum of 1.923 Gbps. Due to the low-voltage swing of the LVDS I/O standard, the electromagnetic interference (EMI) effects are much smaller than CMOS, TTL, and PECL. This low EMI makes LVDS ideal for applications with low EMI requirements or noise immunity requirements. The LVDS standard specifies a differential output voltage range of 250 mV VOD 550 mV. The Cyclone device family meets the ANSI/TIA/EIA-644 standard and is LVDS-compatible but, unlike previous products with LVDS support, Cyclone does not have dedicated SERDES or LVDS drivers. While external resistors are required for LVDS output support, Cyclone does have direct LVDS-compatible input support throughout the chip. This flexible approach to LVDS support allows LVDS compatibility on every bank of the Cyclone chip at speeds up to 311Mbps. (Contact Altera Applications for the latest LVDS specification). Altera Corporation May 2003 8-7 Preliminary Cyclone Device Handbook, Volume 1 Differential SSTL-2 - EIA/JEDEC Standard JESD8-9A The differential SSTL-2 I/O standard is a 2.5-V standard used for applications such as high-speed DDR SDRAM clock interfaces. This standard supports differential signals in systems using the SSTL-2 standard and supplements the SSTL-2 standard for differential clocks. The differential SSTL-2 standard specifies an input voltage range of - 0.3 V VI VCCIO + 0.3-V. The differential SSTL-2 standard does not require an input reference voltage differential. See Figure 8-5 for details on differential SSTL-2 termination. Cyclone devices support output clock levels for differential SSTL-2 class II operation. Figure 8-5. SSTL-2 Class II Differential Termination VTT = 1.25 V VTT = 1.25 V VTT = 1.25 V VTT = 1.25 V Differential Transmitter 50 25 50 50 50 Differential Receiver Z0 = 50 25 Z0 = 50 f See Section I, Cyclone FPGA Family Data Sheet for more details on the I/O Standards discussed in this section. The I/O pins on Cyclone devices are grouped together into I/O banks and each bank has a separate power bus. This permits designers to select the preferred I/O standard for a given bank enabling tremendous flexibility in the Cyclone device's I/O support. Each Cyclone device supports four I/O banks regardless of density. Similarly, each device I/O pin is associated with one of these specific, numbered I/O banks. To accommodate voltage-referenced I/O standards, each Cyclone I/O bank has a common VREF bus and each bank supports 3 VREF pins (see Figure 8-6). In the event these pins are not used as VREF pins, they may be used as regular I/O pins. Cyclone I/O Banks 8-8 Preliminary Altera Corporation May 2003 Cyclone I/O Banks Figure 8-6. Cyclone Power Bank & VREF Arrangement VREF2B2 VREF1B2 VREF0B2 B2 VREF0B1 VREF0B3 VREF1B1 VREF2B1 B4 VREF2B4 VREF1B4 VREF0B4 Additionally, each Cyclone I/O bank has its own VCCIO pins. Any single I/O bank must have only one VCCIO setting from among 1.5-V, 1.8-V, 2.5-V or 3.3-V. Although there can only be one VCCIO voltage, Cyclone devices permit additional input signaling capabilities as shown in Table 8-2. Table 8-2. Acceptable Input Levels for LVTTL/LVCMOS Acceptable Input Levels Bank VCCIO 3.3-V 2.5-V 1.8-V 1.5-V 3.3-V v v v v 2.5-V v v v v 1.8-V 1.5-V v v v Altera Corporation May 2003 8-9 Preliminary VREF2B3 VREF1B3 B1 B3 Cyclone Device Handbook, Volume 1 f For more information on acceptable input levels, see Chapter 11, Using Cyclone Devices in Multiple-Voltage Systems. Any number of supported single-ended or differential standards can be simultaneously supported in a single I/O bank as long as they use compatible VCCIO levels for input and output pins. For example, an I/O bank with a 2.5-V VCCIO setting can support 2.5-V LVTTL inputs and outputs, 2.5-V LVDS-compatible inputs and outputs, and 3.3-V LVCMOS inputs only. Voltage-referenced standards can be supported in an I/O bank using any number of single-ended or differential standards as long as they use the same VREF and a compatible VCCIO value. For example, if you choose to implement both SSTL-3 and SSTL-2 in your Cyclone device, I/O pins using these standards--because they require different VREF values--must be in different banks from each other. However, SSTL-3 and 3.3-V LVCMOS could be supported in the same bank with the VCCIO set to 3.3-V and the VREF set to 1.5-V. f See "Pad Placement & DC Guidelines" on page 8-13 for more information. All four I/O banks support all of the I/O standards with the exception of PCI, which is only supported on banks 1 and 3 (see Figure 8-7). 8-10 Preliminary Altera Corporation May 2003 Programmable Current Drive Strength Figure 8-7. I/O Standards Supported in Cyclone Devices I/O Bank 2 Notes (1), (2) I/O Bank 1 also supports the 3.3-V PCI I/O Standard All I/O Banks support 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS LVDS SSTL-2 Class I and II SSTL-3 Class I and II I/O Bank 3 also supports the 3.3-V PCI I/O Standard I/O Bank 1 I/O Bank 4 Notes to Figure 8-7 (1) (2) PCI is not supported on the EP1C3 device. The EP1C3 device in the 100-pin thin quad flat pack (TQFP) package does not have support for a PLL LVDScompatible input or an external clock output. Programmable Current Drive Strength The Cyclone device I/O standards support various output current drive settings as shown in Table 8-3. These programmable drive-strength settings are a valuable tool in helping decrease the effects of simultaneously switching outputs (SSO) in conjunction with reducing system noise. The supported settings ensure that the device driver meets the specifications for IOH and IOL of the corresponding I/O standard. These drive-strength settings are programmable on a per-pin basis (for output and bidirectional pins only) using the Quartus II software. To modify the current strength of a particular pin, see "Programmable Drive Strength Settings". Altera Corporation May 2003 I/O Bank 3 8-11 Preliminary Cyclone Device Handbook, Volume 1 Table 8-3. Programmable Drive Strength I/O Standard 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS SSTL-3 class I and II SSTL-2 class I and II IOH/IOL Current Strength Setting 24, 16, 12, 8, 4 mA 12, 8, 4, 2 mA 16, 12, 8, 2 mA 12, 8, 2 mA 8, 4, 2 mA Minimum strength Minimum strength Hot Socketing Cyclone devices support any power-up or power-down sequence (VCCIO and VCCINT) to facilitate hot socketing. You can drive signals into the device before or during power-up or power-down without damaging the device. Cyclone devices will not drive out until the device is configured and has attained proper operating conditions. You can power up or power down the VCCIO and VCCINT pins in any sequence. The power supply ramp rates can range from 100 ns to 100 ms and I/O pins can be driven by active signals with rise/fall times of 2ns to 40ns. Additionally, during power-up, the I/O pin capacitance is less than 15 pF and the clock pin capacitance is less than 20pF. The hot socketing DC specification is | IIOPIN | < 300 A. The hot socketing AC specification is | IIOPIN | < 8 mA for 10 ns or less. I/O Termination The majority of the Cyclone I/O standards are single-ended, nonvoltage-referenced I/O standards and, as such, the following I/O standards do not specify a recommended termination scheme: 3.3-V LVTTL / LVCMOS 2.5-V LVTTL / LVCMOS 1.8-V LVTTL / LVCMOS 1.5-V LVCMOS 3.3-V PCI The Cyclone device family does not feature on-chip I/O termination resistors. 8-12 Preliminary Altera Corporation May 2003 Pad Placement & DC Guidelines Voltage-Referenced I/O Standard Termination Voltage-referenced I/O standards require both an input reference voltage, VREF, and a termination voltage, VTT. The reference voltage of the receiving device tracks the termination voltage of the transmitting device. f For more information on termination for voltage-referenced I/O standards, see "Supported I/O Standards" on page 8-2. Differential I/O Standard Termination Differential I/O standards typically require a termination resistor between the two signals at the receiver. The termination resistor must match the differential load impedance of the bus. LVDS is the only differential I/O standard supported by Cyclone devices. For information on LVDS termination, contact Altera Applications. Pad Placement & DC Guidelines This section provides pad placement guidelines for the programmable I/O standards supported by Cyclone devices and includes essential information for designing systems using the devices' selectable I/O capabilities. This section also discusses the DC limitations and guidelines. Differential Pad Placement Guidelines In order to maintain an acceptable noise level on the VCCIO supply, there are restrictions on placement of single-ended I/O pads in relation to differential pads. Use the following guidelines for placing single-ended pads with respect to differential pads in Cyclone devices. Single-ended inputs may be only be placed four or more pads away from a differential pad. Single-ended outputs and bidirectional pads may only be placed five or more pads away from a differential pad. The Quartus II software generates an error message for illegally placed pads. 1 VREF Pad Placement Guidelines In order to maintain an acceptable noise level on the VCCIO supply and to prevent output switching noise from shifting the VREF rail, there are restrictions on the placement of single-ended voltage referenced I/Os with respect to VREF pads and VCCIO/GND pairs. Please use the following guidelines for placing single-ended pads in Cyclone devices. Altera Corporation May 2003 8-13 Preliminary Cyclone Device Handbook, Volume 1 Input Pads Each VREF pad supports a maximum of 40 input pads with up to 20 on each side of the VREF pad. This is irrespective of VCCIO/GND pairs. Output Pads When a voltage referenced input or bidirectional pad does not exist in a bank, there is no limit to the number of output pads that can be implemented in that bank. When a voltage referenced input exists, each VCCIO/GND pair supports 9 outputs for Fineline BGA(R) packages or 4 outputs for quad flat pack (QFP) packages. Any output pads must be placed greater then 2 pads away from your VREF pad to maintain acceptable noise levels. Bidirectional Pads Bidirectional pads must satisfy input and output guidelines simultaneously. If the bidirectional pads are all controlled by the same OE and there are no other outputs or voltage referenced inputs in the bank, then there is no case where there is a voltage referenced input active at the same time as an output. Therefore, the output limitation does not apply. However, since the bidirectional pads are linked to the same OE, the bidirectional pads will all act as inputs at the same time. Therefore, the input limitation of 40 input pads (20 on each side of your VREF pad) will apply. If the bidirectional pads are all controlled by different output enables (OE) and there are no other outputs or voltage referenced inputs in the bank, then there may be a case where one group of bidirectional pads is acting as inputs while another group is acting as outputs. In such cases, apply the formulas shown in Table 8-4. Table 8-4. Input-Only Bidirectional Pad Limitation Formulas Package Type FineLine BGA Formula (Total number of bidirectional pads) - (Total number of pads from the smallest group of pads controlled by an OE) 9 (per VCCIO/GND pair) (Total number of bidirectional pads) - (Total number of pads from the smallest group of pads controlled by an OE) 4 (per VCCIO/GND pair). QFP 8-14 Preliminary Altera Corporation May 2003 Pad Placement & DC Guidelines Consider an FineLine BGA package with 4 bidirectional pads controlled by OE1, 4 bidirectional pads controlled by OE2, and 2 bidirectional pads controlled by OE3. If OE1 and OE2 are active and OE3 is inactive, there are 10 bidirectional pads, but it is safely allowable because there would be 8 or fewer outputs per VCCIO/GND pair. When at least one additional voltage referenced input and no other outputs exist in the same VREF bank, the bidirectional pad limitation applies in addition to the input and output limitations. See the following equation. (Total number of bidirectional pads) + (Total number of input pads) 40 (20 on each side of your VREF pad) 1 The bidirectional pad limitation applies to both Fineline BGA packages and QFP packages. After applying the equation above, apply one of the equations in Table 8-5, depending on package type. Table 8-5. Bidirectional Pad Limitation Formulas (Where VREF Inputs Exist) Package Type FineLine BGA QFP Formula (Total number of bidirectional pads) 9 (per VCCIO/GND pair) (Total number of bidirectional pads) 4 (per VCCIO/GND pair) When at least one additional output exists but no voltage referenced inputs exist, apply the appropriate formula from Table 8-6. Table 8-6. Bidirectional Pad Limitation Formulas (Where VREF Outputs Exist) Package Type FineLine BGA Formula (Total number of bidirectional pads) + (Total number of additional output pads) - (Total number of pads from the smallest group of pads controlled by an OE) 9 (per VCCIO/GND pair) (Total number of bidirectional pads) + (Total number of additional output pads) - (Total number of pads from the smallest group of pads controlled by an OE) = 4 (per VCCIO/GND pair) QFP Altera Corporation May 2003 8-15 Preliminary Cyclone Device Handbook, Volume 1 When additional voltage referenced inputs and other outputs exist in the same VREF bank, then the bidirectional pad limitation must again simultaneously adhere to the input and output limitations. As such, the following rules apply: Total number of bidirectional pads + Total number of input pads 40 (20 on each side of your VREF pad). 1 The bidirectional pad limitation applies to both Fineline BGA packages and QFP packages. After applying the equation above apply one of the equations in Table 8-7, depending on package type. Table 8-7. Bidirectional Pad Limitation Formulas (Multiple VREF Inputs & Outputs) Package Type FineLine BGA QFP Formula (Total number of bidirectional pads) + (Total number of output pads) 9 (per VCCIO/GND pair) Total number of bidirectional pads + Total number of output pads 4 (per VCCIO/GND pair) Each I/O bank can only be set to a single VCCIO voltage level and a single VREF voltage level at a given time. Pins of different I/O standards can share the bank if they have compatible VCCIO values (see Table 8-2 for more details). In all cases listed above, the Quartus II software generates an error message for illegally placed pads. DC Guidelines There is a current limit of 320 mA per 10 consecutive output pins, as shown by the following equation: pin + 9 pin Ipin < 320 mA Table 8-8 shows the current allowed per pin by select I/O standards as measured under the standard's defined loading conditions. PCI, LVTTL, LVCMOS, and other supported I/O standards not shown in the table do 8-16 Preliminary Altera Corporation May 2003 Quartus II Software Support not have standardized loading conditions. As such, the current allowed per pin in a series-loaded condition for these standards is considered negligible. Table 8-8. I/O Standard DC Specification I Pin (mA) Pin I/O Standard 3.3-V VCCIO SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II LVDS 8 16 N/A N/A N/A 2.5-V VCCIO N/A N/A 8.1 16.4 Quartus II Software Support Use the Quartus II software to specify which programmable I/O standards to use for Cyclone devices. This section describes Quartus II implementation, placement, and assignment guidelines, including: Compiler settings Device & pin options Assigning pins Programmable drive strength settings I/O banks in the floorplan view Auto placement & verification Compiler Settings The Compiler Settings dialog box (Processing menu) includes options allowing you to set a default I/O standard, optimize for I/O placement, assign I/O pins, and numerous other I/O-related options. The most pertinent user features are described in detail below. Device & Pin Options To access Device & Pin Options, choose Compiler Settings (Processing menu), then choose the Chips and Devices tab. There are numerous categories in the Device & Pin Options dialog box, including General, Configuration, Programming Files, Unused Pins, Dual-Purpose Pins, and Voltage. Similarly, each of these categories contains settings vital to the device operation such as the default I/O standard applied to the chip (Voltage tab), how to reserve all unused pins (Unused Pins tab), and whether or not the device should enable a device-wide reset (General tab). Altera Corporation May 2003 8-17 Preliminary Cyclone Device Handbook, Volume 1 Assigning Pins Assuming a specific device has been chosen in the available devices list in the Compiler Settings dialog box, clicking Assign Pins provides the device's pin settings and pin assignments (see Figure 8-8). You can view, add, remove and update pin settings under the Available Pins & Existing Assignments section within this window. The information for each pin includes: Number Name I/O bank I/O standard Type (e.g., row or column I/O and differential or control) SignalProbe Source Name Enabled (i.e., whether SignalProbe routing is enabled or disabled status) Figure 8-8. Assign Pins 1 While assigned and unassigned pins are displayed in the Assign Pins dialog box, note that this listing does not include dedicated pins. Consult the device pin-out table for a completing listing of pins including dedicated pins. When you assign an I/O standard that requires a reference voltage to an I/O pin, the Quartus II software automatically assigns VREF pins. Refer to Quartus II Help for instructions on how to use an I/O standard for a pin. 8-18 Preliminary Altera Corporation May 2003 Quartus II Software Support Programmable Drive Strength Settings To specify programmable drive strength settings, perform the following steps: 1. 2. Choose Assignment Organizer (Tools menu). Choose the Edit specific entity & node settings for: setting, then select the output or bidirectional pin for which you will specify the current strength. Select Options for Individual Nodes Only in the Assignment Categories dialog box. Select Click here to add a new assignment. In the Assignment dialog box, set the Name field to Current Strength then enter the desired value in the Setting field. Click Add. Click Apply then OK. 3. 4. 5. 6. 7. Note that the Quartus II software displays the entire range of drive strength choices. While the Quartus II software does not prohibit you from specifying any of these for your I/O pin, not every setting is supported by every I/O standard. Please refer to Table 8-3 for supported combinations. I/O Banks in the Floorplan View View the arrangement of the device I/O banks by choosing Interior Cells (View menu) with the Floorplan View displayed (see Figure 8-9). Pins that belong to the same I/O bank must use the same VCCIO voltage. You can assign multiple I/O standards to the I/O pins in any given I/O bank as long as the VCCIO voltage of the desired I/O standards is the same. A given bank can have up to three VREF signals, and each signal can support one voltage-referenced I/O standard. Each device I/O pin belongs to a specific, numbered I/O bank. By default, the Show I/O Banks option is enabled, allowing the I/O banks to be displayed as color coded (See Figure 8-9). Altera Corporation May 2003 8-19 Preliminary Cyclone Device Handbook, Volume 1 Figure 8-9. Floorplan View Window Auto Placement & Verification of Selectable I/O Standards The Quartus II software automatically verifies the placement for all I/O and VREF pins and performs the following actions: Automatically places I/O pins of different VREF standards without pin assignments in separate I/O banks and enables the VREF pins of these I/O banks. Verifies that voltage-referenced I/O pins requiring different VREF levels are not placed in the same bank. Reports an error message if the current limit is exceeded for a Cyclone power bank (See "DC Guidelines"). Automatically assigns VREF pins and I/O pins such that the current requirements are met and I/O standards are placed properly. Conclusion Cyclone device I/O capabilities enable system designers to keep pace with increasing design complexity utilizing a low-cost FPGA device family. Support for I/O standards including SSTL and LVDS compatibility allow Cyclone devices to fit into a wide variety of applications. The Quartus II software makes it easy to use these I/O standards in Cyclone device designs. After design compilation, the software also provides clear, visual representations of pads and pins and 8-20 Preliminary Altera Corporation May 2003 More Information the selected I/O standards. Taking advantage of the support of these I/O standards in Cyclone devices will allow you to lower your design costs without compromising design flexibility or complexity. More Information For more information on Cyclone devices refer to the following resources: Section I, Cyclone FPGA Family Data Sheet Chapter 11, Using Cyclone Devices in Multiple-Voltage Systems Application Note 75: High-Speed Board Layout Guidelines References For more information on the I/O standards referred to in this document, see the following sources: Stub Series Terminated Logic for 2.5-V (SSTL-2), JESD8-9A, Electronic Industries Association, December 2000. 1.5-V +/- 0.1-V (Normal Range) and 0.9-V - 1.6-V (Wide Range) Power Supply Voltage and Interface Standard for Non-terminated Digital Integrated Circuits, JESD8-11, Electronic Industries Association, October 2000. 1.8-V +/- 0.15-V (Normal Range) and 1.2-V - 1.95-V (Wide Range) Power Supply Voltage and Interface Standard for Non-terminated Digital Integrated Circuits, JESD8-7, Electronic Industries Association, February 1997. 2.5-V +/- 0.2-V (Normal Range) and 1.8-V to 2.7-V (Wide Range) Power Supply Voltage and Interface Standard for Non-terminated Digital Integrated Circuits, JESD8-5, Electronic Industries Association, October 1995. Interface Standard for Nominal 3-V/ 3.3-V Supply Digital Integrated Circuits, JESD8-B, Electronic Industries Association, September 1999. PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group, December 1998. Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, ANSI/TIA/EIA-644, American National Standards Institute/Telecommunications Industry/Electronic Industries Association, October 1995. Altera Corporation May 2003 8-21 Preliminary Cyclone Device Handbook, Volume 1 8-22 Preliminary Altera Corporation May 2003 9. Implementing LVDS in Cyclone Devices C51009-1.0 Introduction From high-speed backplane applications to high-end switch boxes, LVDS is the technology of choice. LVDS is a low-voltage differential signaling standard, allowing higher noise immunity than single-ended I/O technologies. Its low-voltage swing allows for high-speed data transfers, low power consumption, and less electromagnetic interference (EMI). LVDS I/O signaling is a data interface standard defined in the TIA/EIA-644 and IEEE Std. 1596.3 specifications. Altera(R) CycloneTM devices allow you to transmit and receive data through LVDS signals at a data rate up to 311 megabits per second (Mbps). For the LVDS transmitter and receiver, the Cyclone device's input and output pins support serialization and deserialization through internal logic. This application note describes how to use Cyclone I/O pins for LVDS signaling and contains the following topics: Cyclone LVDS I/O Banks Cyclone LVDS I/O Interface Cyclone Receiver & Transmitter Termination Implementing Cyclone LVDS I/O Pins in the Quartus II Software Design Guidelines Cyclone LVDS I/O Banks Cyclone devices offer four I/O banks, as shown in Figure 9-1. A subset of pins in each of the four I/O banks (on both rows and columns) support the LVDS interface. Cyclone pin tables list the pins that support the LVDS I/O interface. The EP1C3 device in the 100-pin thin quad flat pack (TQFP) package does not support the LVDS I/O interface. Altera Corporation May 2003 9-1 Preliminary Cyclone Device Handbook, Volume 1 Figure 9-1. Cyclone I/O Banks I/O Bank 2 I/O Bank 1 Also Supports the 3.3-V PCI I/O Standard I/O Bank 1 All I/O Banks Support 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS LVDS SSTL-2 Class I and II SSTL-3 Class I and II I/O Bank 3 Also Supports the 3.3-V PCI I/O Standard I/O Bank 3 Individual Power Bus I/O Bank 4 Table 9-1 shows the total number of supported LVDS channels in each Cyclone device. You can use each channel as a receiver or transmitter. Cyclone devices support different modes (ranging from x 1 to x 10) of operation with a maximum internal clock frequency of 311 MHz and a maximum data rate of 311 Mbps. 9-2 Preliminary Altera Corporation May 2003 Cyclone LVDS I/O Interface Table 9-1. Number of LVDS Channels Per Cyclone Device Device EP1C3 EP1C4 Pin Count 144 324 400 Total Number of LVDS Channels 34 103 129 29 72 72 66 72 103 95 129 EP1C6 144 240 256 EP1C12 240 256 324 EP1C20 324 400 f For more information on I/O standards supported by Cyclone devices, see Chapter 8, Using Selectable I/O Standards in Cyclone Devices. You can use the I/O pins and internal logic to implement an LVDS receiver and transmitter in Cyclone devices. Cyclone devices do not contain dedicated serialization or deserialization circuitry; therefore, shift registers, internal global phase-locked loops (PLLs), and I/O cells are used to perform serial-to-parallel conversions on incoming data and parallel-to-serial conversion on outgoing data. Cyclone LVDS I/O Interface Clock Domains Cyclone devices provide a global clock network and two PLLs (the EP1C3 device only contains one PLL). The global clock network consists of eight global clock lines that drive through the entire device (see Figure 9-2). There are four dedicated clock pins that feed the PLL inputs (two dedicated clocks for each PLL). PLL pins can also act as LVDS input pins. Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as external outputs for LVDS differential I/O support. Altera Corporation May 2003 9-3 Preliminary Cyclone Device Handbook, Volume 1 Figure 9-2. Cyclone Global Clock Network DPCLK2 Note (1) DPCLK3 Cyclone Device Global Clock Network 8 DPCLK1 From logic array 4 From logic array 4 DPCLK4 CLK0 CLK1 (3) PLL1 2 4 4 2 PLL2 (2) CLK2 CLK3 DPCLK0 DPCLK5 DPCLK7 DPCLK6 Notes to Figure 9-2: (1) (2) (3) The EP1C3 device in the 100-pin TQFP package has five DPCLK pins (DPCLK2, DPCLK3, DPCLK4, DPCLK6, and DPCLK7). EP1C3 devices only contain one PLL (PLL1). EP1C3 devices in the 100-pin TQFP package do not support differential clock inputs or outputs. LVDS Receiver & Transmitter Figure 9-3 shows a simple point-to-point LVDS application where the source of the data is a LVDS transmitter. These LVDS signals are typically transmitted over a pair of printed circuit board (PCB) traces, but a combination of a PCB trace, connectors, and cables is a common application setup. 9-4 Preliminary Altera Corporation May 2003 Cyclone LVDS I/O Interface Figure 9-3. Typical LVDS Application Cyclone Device Transmitting Device txout + rxin + 100 txout rxin txout Cyclone Logic Array txout + 120 120 rxin + 170 rxin 100 Receiving Device Input Buffer Output Buffer The Cyclone LVDS I/O pins meet the IEEE 1596 LVDS specification. Figures 9-4 and 9-5 show the signaling levels for LVDS receiver inputs and transmitter outputs. Figure 9-4. Receiver Input Waveform for the Differential I/O Standard Differential Waveform Positive Channel (p) +VID -VID VOS Negative Channel (n) Ground Single-Ended Waveform +VID p-n=0V VID (Peak-to-Peak) -VID Altera Corporation May 2003 9-5 Preliminary Cyclone Device Handbook, Volume 1 Figure 9-5. Transmitter Output Waveform for Differential I/O Standard Differential Waveform Positive Channel (p) +VOD -VOD VOS Negative Channel (n) Ground Single-Ended Waveform +VOD p-n=0V VSS (1) -VOD Note to Figure 9-5: (1) VSS: steady-state differential output voltage. Table 9-2 lists the LVDS I/O specifications. Table 9-2. LVDS I/O Specifications Symbol VCCINT VCCIO VOD VOD VOS VOS VTH VIN RL Parameter Supply Voltage I/O Supply Voltage Conditions Min 1.425 2.375 250 Typ 1.5 2.5 Max 1.575 2.625 550 50 Unit V V mV mV V mV mV V W Differential Output RL = 100 Voltage Change in VOD between H and L Output Offset Voltage Change in VOS between H and L Differential Input Threshold Receiver input voltage range Receiver Differential Input Resistor RL = 100 RL = 100 RL = 100 VCM = 1.2 V 1.125 1.25 1.375 50 -100 0 90 100 100 2.4 110 9-6 Preliminary Altera Corporation May 2003 Cyclone LVDS I/O Interface LVDS Timing in Cyclone Devices Since LVDS enables data transmission at very high speed, LVDS timing analysis is different than other I/O standards. You must understand how to analyze timing for the LVDS signal, which is based on skew between the data and the clock signal. You should also consider board skew, cable skew, and clock jitter in your calculation. This section briefly explains the LVDS timing parameter in Cyclone devices. Table 9-3 defines the parameters of the timing diagram shown in Figure 9-6. Table 9-3. LVDS Timing Definition Parameter SW Definition Sampling Window Channel-toChannel Skew Description Period of time input data must be stable so it can be successfully sampled by the receiver. Difference between the fastest and slowest data output transitions, which include clock-to-output (tCO) and clock skew of the transmitter. Total margin left after accounting for SW and TCCS. TCCS RSKM Receiver Input Skew Margin Figure 9-6. LVDS Timing Diagram External Input Clock Time Unit Interval (TUI) Internal Clock TCCS RSKM Sampling Window (SW) RSKM TCCS Receiver Input Data Figure 9-7 shows the LVDS timing budget. Altera Corporation May 2003 9-7 Preliminary Cyclone Device Handbook, Volume 1 Figure 9-7. Cyclone LVDS Timing Budget Internal Clock Period Note (1) 0.5 x TCCS RSKM SW RSKM 0.5 x TCCS Note to Figure 9-7: (1) The equation for the LVDS timing budget is: Period = 0.5 x TCCS + RSKM + SW + RSKM + 0.5 x TCCS. Table 9-4 shows the preliminary timing budget for Cyclone devices at 311 Mbps. Table 9-4. Preliminary Timing Budget for Cyclone LVDS at 311 Mbps Parameter Period SW TCCS RSKM Time (ns) 3.22 1.20 1.02 0.50 1 This application note will be updated with actual silicon data after device characterization is complete. Cyclone Receiver & Transmitter Termination Receiving LVDS signals on Cyclone I/O pins is straightforward, and can be done by assigning LVDS to desired pins in the Quartus II software. A 100- parallel terminator is required at the receiver input pin, as shown in Figure 9-8. 9-8 Preliminary Altera Corporation May 2003 Cyclone Receiver & Transmitter Termination Figure 9-8. Termination Scheme on Cyclone LVDS Receiver LVDS Transmitter Cyclone Receiver + In Driver Z0 = 50 100 Z0 = 50 + Receiver Out f For PCB layout guidelines, refer to Application Note 224: High-Speed Board Layout Guidelines. Cyclone LVDS transmitter signals are generated using a resistor network, as shown in Figure 9-9 (with RS= 120 and RDIV = 170 ). The resistor network attenuates the driver outputs to levels similar to the LVDS signaling, which is recognized by LVDS receivers with minimal effect on 50- trace impedance. Figure 9-9. Termination Scheme on Cyclone LVDS Transmitter Core Resistor Network 120 Z0 = 50 In 120 170 Z0 = 50 100 + Receiver Out VCCIO = 2.5 V Altera Corporation May 2003 9-9 Preliminary Cyclone Device Handbook, Volume 1 Implementing Cyclone LVDS I/O Pins in the Quartus II Software For differential signaling, the receiver must deserialize the incoming data and send it to the internal logic as a parallel signal. Accordingly, the transmitter must serialize the parallel data coming from the internal logic to send it off-chip (see Figure 9-10). Figure 9-10. Deserialization & Serialization at Receiver & Transmitter Cyclone Device Receiver rxin + Transmitter txout + Serial Data Serial Data rxin Deserializer Serializer txout - Although Cyclone devices do not incorporate a dedicated serializer/ deserializer (SERDES), you can incorporate these functions in your design using the Quartus II software. Table 9-5 shows the three different reference design examples discussed in this application note. 1 Reference design examples for EP1C20, EP1C12, EP1C6, and EP1C4 devices have two PLLs per device, whereas EP1C3 devices in the 144-pin TQFP package have only one. Reference design files are listed under the title of this application note on the Altera web site at www.altera.com. Table 9-5. Reference Designs PLL Mode x2 x4 x8 Input Clock Frequency (MHz) 155.50 77.75 38.88 Transmitting Serial Data on Cyclone LVDS Outputs The LVDS transmitter reference design allows the data and clock frequency to be simultaneously transmitted. Figure 9-11 shows the circuit schematic of a reference design for serialization of an 8-bit parallel bus implemented in EP1C20, EP1C12, EP1C6, and EP1C4 devices. 9-10 Preliminary Altera Corporation May 2003 Implementing Cyclone LVDS I/O Pins in the Quartus II Software Figure 9-12 shows the x 8 mode serialization circuitry implementation in EP1C3 devices. You can modify reference designs for desired serialization. Figure 9-11. Reference Design Schematic for x 8 Mode Serializer Implemented for EP1C20, EP1C12 & EP1C6 Devices Altera Corporation May 2003 9-11 Preliminary Cyclone Device Handbook, Volume 1 Figure 9-12. Reference Design Schematic for x 8 Mode Serializer Implemented for EP1C3 Devices (144Pin TQFP Package) In Figures 9-11 and 9-12, the D-type flipflops (D_FF) are used to register the parallel data, and a Cyclone PLL is used to multiply the core logic clock frequency. Cyclone PLLs provide clock synthesis for PLL output ports using M/(N x post- scalar) scaling factors. A shift register is used to convert the parallel-to-serial data stream, and a counter and a comparator are used to determine the byte boundary. 9-12 Preliminary Altera Corporation May 2003 Implementing Cyclone LVDS I/O Pins in the Quartus II Software Transmitter Circuit The input and output signals and their function in the sample transmitter design are listed in Tables 9-6 and 9-7. Table 9-6. LVDS Input Pins (LVDS_TX) Pin data[7..0] clk 8 bits of parallel inputs. PLL input clock. If x8 mode is used, the input clock frequency is 38.88 MHz; for x4 mode, the input frequency is 77.75 MHz; and for x2 mode, the input frequency is 155.5 MHz. Active-high reset signal. This pin is driven high at the beginning of operation. Description reset Table 9-7. LVDS Output Pins (LVDS_TX) Pin dataout clkout Description The data rate is 311 Mbps. You can choose whether to have a fast clock as the clock out (311 MHz), or a slow clock as the clock out (38.88 MHz for x8 mode, 77.75 MHz for x4 mode, or 155.5 MHz for x2 mode). The frequency is dependent on the input clock frequency required on the receiver of the transmitted data. The clock out frequency in this reference design is 311 MHz. Modify the design if another output clock frequency is desired. Table 9-8 lists the modules used in the circuit and their corresponding functions or purpose. Table 9-8. Transmitter Circuit Modules (Part 1 of 2) Module PARALLEL_REG PLL Description Consists of eight registers, each is connected to one bit of data input. The slow clock from the PLL is used to register the data. Input of the PLL is the input clk signal. In the x8 mode design, the frequency is 38.88 MHz. Therefore, the PLL outputs are c0 at 311 MHz and c1 at 38.88 MHz. If needed, you can use the PLL locked signal. This parallel-in-serial-out SHIFT_REG acts as a serializer. The PLL output c0 clocks SHIFT_REG at 311 MHz. Consequently, the serial output of the shift register can be transmitted at 311 Mbps. The best location for the shift register is the logic array block (LAB) adjacent to the dataout pin. SHIFT_REG Altera Corporation May 2003 9-13 Preliminary Cyclone Device Handbook, Volume 1 Table 9-8. Transmitter Circuit Modules (Part 2 of 2) Module COUNTER COMPARE7 Description The counter is enabled after the first rising edge of the slow clock c1. The counter and comparator are used to determine the byte boundary. COMPARE7 is a comparator. When the input of COMPARE7 is d'7, it will drive out high. The output of COMPARE7 is the load signal of the parallel-in-serial-out shift register. To register the data before driving off chip, use the register in the input/output element (IOE) of the output pin. This counter is used in EP1C3 devices only. Since EP1C3 devices have only one PLL, this counter is used as a divider to produce the slow clock c1. D_FF CTR_8 Capturing Serial Data on Cyclone LVDS Inputs Cyclone devices do not incorporate a dedicated deserializer to capture the serial stream data and clock. However, you can design a deserializer using the Quartus II software. Figure 9-13 shows a reference design for a deserializer circuit implemented in EPC1C20, EP1C12, EP1C6, and EP1C4 devices. Figure 9-14 shows the x 8 mode deserializer circuitry implemented in EP1C3 devices. Figure 9-13. Reference Design Schematic for Receiver Deserializer Implemented in EP1C20, EP1C12, EP1C6 & EP1C4 Devices 9-14 Preliminary Altera Corporation May 2003 Implementing Cyclone LVDS I/O Pins in the Quartus II Software Figure 9-14. Reference Design Schematic for Receiver Deserializer Implemented in EP1C3 Devices Receiver Circuit The input and output signals and their function in a sample receiver design are listed in Tables 9-9 and 9-10. Table 9-9. LVDS Input Pins (LVDS_RX) Pin data_i clk Description Incoming serial stream of data. PLL input clock. If x8 mode is used, the input clock frequency is 38.88 MHz; for x4 mode, the input frequency is 77.75 MHz; and for x2 mode, the input frequency is 155.5 MHz. Active-high reset signal. This pin is driven high at the beginning of operation. reset Table 9-10. LVDS Output Pins (LVDS_RX) Pin out_rx[7..0] c1/clkdiv8 Description Output bus (8 bits in x8 mode). Slower PLL output clock which goes to internal logic. If x8 mode is used, the input clock frequency is 38.88 MHz; for x4 mode, the input frequency is 77.75 MHz; and for x2 mode, the input frequency is 155.5 MHz. Altera Corporation May 2003 9-15 Preliminary Cyclone Device Handbook, Volume 1 Table 9-11 lists the modules used in the circuit and their corresponding functions or purpose. Table 9-11. Receiver Circuit Modules Module D_FF Description Captures the incoming serial stream data. PLL output c0 (311 MHz) is inverted to sample the LVDS receiver data in the middle of the data eye. The register is placed in the IOE of the data_i pin. Input of the PLL is the input clk signal. PLL output c0 (311 MHz) clocks SHIFT_REG and the inverted c0 clocks D_FF. PLL output c1 (38.88 MHz) provides the clock for PARALLEL_REG. Serial-in-parallel-out shift register. Consists of eight D_FF modules. Converts the serial data from 311 Mbps to eight bits of parallel data clocked at 38.88 MHz. The best location for the shift register is the LAB adjacent to the data_i pin. Consists of eight registers, each is connected to one bit of data input. The slow clock from the PLL (c1) is used to clock the parallel register. This counter is used in only EP1C3 devices. Since EP1C3 devices have only one PLL, this counter is used as a divider to produce the slow clock. PLL SHIFT_REG PARALLEL_REG CTR_8 Design Guidelines To implement LVDS in Cyclone devices, adhere to the following design guidelines in the Quartus II software. Route LVDS CLKOUT to pins through regular user LVDS pins. This routing provides better TCCS margin. To meet the tSU and tCO timing requirement between serial and parallel registers, use the I/O registers of the input and output pins. fMAX is limited by the delay between the IOE and the next logic element (LE) register. To achieve an fMAX of 311 MHz, the delay between the IOE and the next LE register at the receiver and transmitter side must not be more than 3.215 ns. The best location to implement the shift registers is within the LAB adjacent to the input or output pin. LVDS data and clock should be aligned at the output pin. If these signals are not aligned, use a phase shift to align them. The Cyclone LVDS reference design did not need this delay since the delay between LVDS clock and data at the pin was negligible. 1 9-16 Preliminary Altera Corporation May 2003 Design Guidelines Differential Pad Placement Guidelines To maintain an acceptable noise level on the VCCIO supply, there are restrictions on placement of single-ended I/O pins in relation to differential pads. Refer to the guidelines in Chapter 8, Using Selectable I/O Standards in Cyclone Devices for placing single-ended pads with respect to differential pads in Cyclone devices. Board Design Considerations This section explains how to get the optimal performance from the Cyclone I/O block and ensure first-time success in implementing a functional design with optimal signal quality. The critical issues of controlled impedance of traces and connectors, differential routing, and termination techniques must all be considered to get the best performance from the integrated circuit (IC). Use this application note together with Section I, Cyclone FPGA Family Data Sheet. The Cyclone device generates signals that travel over the media at frequencies as high as 311 Mbps. Use the following general guidelines: Base board designs on controlled differential impedance. Calculate and compare all parameters such as trace width, trace thickness, and the distance between two differential traces. Maintain equal distance between traces in LVDS pairs, as much as possible. Routing the pair of traces close to each other will maximize the common-mode rejection ratio (CMRR) Longer traces have more inductance and capacitance. These traces should be as short as possible to limit signal integrity issues. Place termination resistors as close to receiver input pins as possible. Use surface mount components. Avoid 90 or 45 corners. Use high-performance connectors. Design backplane and card traces so that trace impedance matches the connector's and/or the termination's impedance. Keep equal number of vias for both signal traces. Altera Corporation May 2003 9-17 Preliminary Cyclone Device Handbook, Volume 1 Create equal trace lengths to avoid skew between signals. Unequal trace lengths result in misplaced crossing points and decrease system margins as the TCCS value increases. Limit vias because they cause discontinuities. Use the common bypass capacitor values such as 0.001 F, 0.01 F, and 0.1 F to decouple the high-speed PLL power and ground planes. Keep switching TTL signals away from differential signals to avoid possible noise coupling. Do not route TTL clock signals to areas under or above the differential signals. Analyze system-level signals. Conclusion Cyclone LVDS I/O capabilities enable you to keep pace with increasing design complexity while offering the lowest-cost FPGA on the market. Support for I/O standards including LVDS allows Cyclone devices to fit into a wide variety of applications. Taking advantage of these I/O standards and Cyclone pricing allows you to lower your design costs while remaining on the cutting edge of technology. 9-18 Preliminary Altera Corporation May 2003 Section V. Design Considerations This section provides documentation on design considerations when utilizing Cyclone devices. In addition to these design considerations, refer to the Intellectual Property section of the Altera web site for a complete offering of IP cores for Cyclone devices. This section contains the following chapters: Chapter 10. Implementing Double Data Rate I/O Signaling in Cyclone Devices Chapter 11. Using Cyclone Devices in Multiple-Voltage Systems Chapter 12. Designing with 1.5-V Devices Revision History The table below shows the revision history for Chapter 10 and 11. Chapter(s) 10 11 12 Date / Version May 2003 v1.0 May 2003 v1.0 May 2003 v1.0 Changes Made Updated text under Figure 10-3. Initial release. Initial handbook release. Altera Corporation Section V-1 Preliminary Design Considerations Cyclone Device Handbook, Volume 1 Section V-2 Preliminary Altera Corporation 10. Implementing Double Data Rate I/O Signaling in Cyclone Devices C51010-1.0 Introduction Double data rate (DDR) transmission is used in many applications where fast data transmission is needed, such as memory access and first-in first-out (FIFO) memory structures. DDR uses both edges of a clock to transmit data, which facilitates data transmission at twice the rate of a single data rate (SDR) architecture using the same clock speed. This method also reduces the number of I/O pins required to transmit data. This application note shows implementations of a double data rate I/O interface using CycloneTM devices. Cyclone devices support DDR input, DDR output, and bidirectional DDR signaling. f For more information on using Cyclone devices in applications with DDR SDRAM and FCRAM memory devices, see "DDR Memory Support" on page 10-4. The DDR input implementation shown in Figure 10-1 uses four internal logic element (LE) registers located in the logic array block (LAB) adjacent to the DDR input pin. The DDR data is fed to the first two of four registers. One register captures the DDR data present during the rising edge of the clock. The second register captures the DDR data present during the falling edge of the clock. Double Data Rate Input Figure 10-1. Double Data Rate Input Implementation DFF ddr D PRN Q DFF D PRN Q ddr_out_h p_edge_reg ddr_h_sync_reg DFF PRN D Q NOT n_edge_reg DFF D PRN Q ddr_out_l ddr_l_sync_reg clk Altera Corporation May 2003 10-1 Preliminary Cyclone Device Handbook, Volume 1 The third and fourth registers synchronize the two data streams to the rising edge of the clock. Figure 10-2 shows examples of functional waveforms from a double data rate input implementation. Figure 10-2. Double Data Rate Input Functional Waveforms clk ddr ddr_out_l ddr_out_h Double Data Rate Output Figure 10-3 shows a schematic representation of double data rate output implemented in a Cyclone device. The DDR output logic is implemented using LEs in the LAB adjacent to the output pin. Two registers are used to synchronize two serial data streams. The registered outputs are then multiplexed by the common clock to drive the DDR output pin at two times the data rate. Figure 10-3. Double Data Rate Output Implementation DFF data_in_h D PRN Q data1 reg_h data0 DFF data_in_l D PRN Q sel result ddr reg_l clk While the clock signal is logic-high, the output from reg_h is driven onto the DDR output pin. While the clock signal is logic-low, the output from reg_l is driven onto the DDR output pin. The DDR output pin can be any available user I/O pin. Figure 10-4 shows examples of functional waveforms from a double data rate output implementation. 10-2 Preliminary Altera Corporation May 2003 Bidirectional Double Data Rate Figure 10-4. Double Data Rate Output Waveforms clk ddr data_in_h data_in_l Bidirectional Double Data Rate Figure 10-5 shows a bidirectional DDR interface, constructed using the DDR input and DDR output examples described in the previous two sections. As with the DDR input and DDR output examples, the bidirectional DDR pin can be any available user I/O pin, and the registers used to implement DDR bidirectional logic are LEs in the LAB adjacent to that pin. The tri-state buffer (TRI) controls when the device drives data onto the bidirectional DDR pin. Figure 10-5. Bidirectional Double Data Rate Implementation ddr_wen DFF ddr_in_h D PRN Q data1 result DFF ddr_in_l PRN D Q data0 sel TRI ddr clk DFF PRN ddr_out_h Q D Q DFF PRN D DFF PRN ddr_out_l Q D Q DFF PRN D NOT Altera Corporation May 2003 10-3 Preliminary Cyclone Device Handbook, Volume 1 Figure 10-6 shows example waveforms from a bidirectional double data rate implementation. Figure 10-6. Double Data Rate Bidirectional Waveforms data_in_h data_in_l ddr_wen clk ddr ddr~result data_out_h data_out_l DDR Memory Support f The Cyclone device family supports both DDR SDRAM and FCRAM memory interfaces up to 133 MHz. For more information on extended DDR memory support in Cyclone devices, see Section I, Cyclone FPGA Family Data Sheet. Utilizing both the rising and falling edges of a clock signal, double data rate transmission is a popular strategy for increasing the speed of data transmission while reducing the required number of I/O pins. Cyclone devices can be used to implement this strategy for use in applications such as FIFO structures, SDRAM/FCRAM interfaces, as well as other time-sensitive memory access and data-transmission situations. Conclusion 10-4 Preliminary Altera Corporation May 2003 11. Using Cyclone Devices in Multiple-Voltage Systems C51011-1.0 Introduction To meet the demand for higher system speed in data communications, semiconductor vendors use increasingly advanced processing technologies requiring lower operating voltages. As a result, printed circuit boards (PCBs) often incorporate devices conforming to one of several voltage level I/O standards, such as 3.3-V, 2.5-V, 1.8-V and 1.5-V. A mixture of components with various voltage level I/O standards on a single PCB is inevitable. In order to accommodate this mixture of devices on a single PCB, a device that can act as a bridge or interface between these devices is needed. The CycloneTM device family's MultiVoltTM I/O operation capability meets the increasing demand for compatibility with devices of different voltages. MultiVolt I/O operation separates the power supply voltage from the output voltage, enabling Cyclone devices to interoperate with other devices using different voltage levels on the same PCB. In addition to MultiVolt I/O operation, this application note discusses several other features that allow you to use Cyclone devices in multiplevoltage systems without damaging the device or the system, including: Hot-Socketing--add and remove Cyclone devices to and from a powered-up system without affecting the device or system operation Power-Up Sequence flexibility--Cyclone devices can accommodate any possible power-up sequence Power-On Reset--Cyclone devices maintain a reset state until voltage is within operating range I/O Standards The I/O buffer of a Cyclone device is programmable and supports a wide range of I/O voltage standards. Each I/O bank in a Cyclone device can be programmed to comply with a different I/O standard. All I/O banks can be configured with the following I/O standards: 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS LVDS SSTL-2 Class I and II SSTL-3 Class I and II Altera Corporation May 2003 11-1 Preliminary Cyclone Device Handbook, Volume 1 I/O banks 1 and 3 also include 3.3-V PCI I/O standard interface capability. See Figure 11-1. Figure 11-1. I/O Standards Supported by Cyclone Devices I/O Bank 2 Notes (1), (2), (3) I/O Bank 1 also supports the 3.3-V PCI I/O Standard I/O Bank 3 also supports the 3.3-V PCI I/O Standard All I/O Banks support 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS LVDS SSTL-2 Class I and II SSTL-3 Class I and II I/O Bank 1 I/O Bank 3 Individual Power Bus I/O Bank 4 Notes to Figure 11-1 (1) (2) (3) Figure 1 is a top view of the silicon die. Figure 1 is a graphical representation only. Refer to the pin list and the Quartus (R) II software for exact pin locations. The EP1C3 device in the 100-pin thin quad flat pack (TQFP) package does not have support for a PLL LVDS input or an external clock output. MultiVolt I/O Operation Cyclone devices include MultiVolt I/O operation capability, allowing the core and I/O blocks of the device to be powered-up with separate supply voltages. The VCCINT pins supply power to the device core and the VCCIO pins supply power the device's I/O buffers. 11-2 Preliminary Altera Corporation May 2003 5.0-V Device Compatibility 1 Supply all device VCCIO pins that have MultiVolt I/O capability at the same voltage level (e.g., 3.3-V, 2.5-V, 1.8-V, or 1.5-V). See Figure 11-2. Figure 11-2. Implementing a Multiple-Voltage System with a Cyclone Device 5.0-V Device Cyclone Device 3.3-V Device 2.5-V Device 5.0-V Device Compatibility A Cyclone device may not correctly interoperate with a 5.0-V device if the output of the Cyclone device is connected directly to the input of the 5.0-V device. If VOUT of the Cyclone device is greater than VCCIO, the PMOS pull-up transistor still conducts if the pin is driving high, preventing an external pull-up resistor from pulling the signal to 5.0-V. A Cyclone device can drive a 5.0-V LVTTL device by connecting the VCCIO pins of the Cyclone device to 3.3 V. This is because the output high voltage (VOH) of a 3.3-V interface meets the minimum high-level voltage of 2.4-V of a 5.0-V LVTTL device. (A Cyclone device cannot drive a 5.0-V LVCMOS device.) Because the Cyclone devices are 3.3-V, 32-bit, 66 MHz PCI compliant the input circuitry accepts a maximum high-level input voltage (VIH) of 4.1-V. To drive a Cyclone device with a 5.0-V device, you must connect a resistor (R2) between the Cyclone device and the 5.0-V device. See Figure 11-3. Altera Corporation May 2003 11-3 Preliminary Cyclone Device Handbook, Volume 1 Figure 11-3. Driving a Cyclone Device with a 5.0-Volt Device Cyclone Device 5.0-V Device 3.0 - 3.4 V 0.25 V 5.0 V 0.25 V V CCIO V CC PCI Clamp V CCIO I Model as R 1 R2 I B If VCCIO is between 3.0-V and 3.6-V and the PCI clamping diode is enabled, the voltage at point B in Figure 11-3 is 4.3-V or less. To limit large current draw from the 5.0-V device, R2 should be small enough for a fast signal rise time and large enough so that it does not violate the highlevel output current (IOH) specifications of the devices driving the trace. The PCI clamping diode in the Cyclone device can support 25mA of current. To compute the required value of R2, first calculate the model of the pullup transistors on the 5.0-V device. This output resistor (R1) can be modeled by dividing the 5.0-V device supply voltage (VCC) by the IOH: R1 = VCC/IOH. Figure 11-4 shows an example of typical output drive characteristics of a 5.0-V device. 11-4 Preliminary Altera Corporation May 2003 5.0-V Device Compatibility Figure 11-4. Output Drive Characteristics of a 5.0-V Device 150 135 120 IOL VCCINT = 5.0V VCCIO = 5.0V Typical IO Output Current (mA) 90 60 IOH 30 1 2 3 4 5 VO Output Voltage (V) As shown above, R1 = 5.0-V/135 mA. 1 The values usually shown in data sheets reflect typical operating conditions. Subtract 20% from the data sheet value for guard band. This subtraction applied to the above example gives R1 a value of 30 . R2 should be selected to not violate the driving device's IOH specification. For example, if the above device has a maximum IOH of 8 mA, given the PCI clamping diode, VIN = VCCIO + 0.7-V = 3.7-V. Given that the maximum supply load of a 5.0-V device (VCC) will be 5.25-V, the value of R2 can be calculated as follows: ( 5.25V - 3.7 V ) - ( 8 mA x 30 ) R 2 = ------------------------------------------------------------------------------------- = 164 8 mA This analysis assumes worst-case conditions. If your system will not see a wide variation in voltage-supply levels, you can adjust these calculations accordingly. 1 Because 5.0-V device tolerance in Cyclone devices requires use of the PCI clamp, and this clamp is activated during configuration, 5.0-V signals may not be driven into the device until it is configured. Altera Corporation May 2003 11-5 Preliminary Cyclone Device Handbook, Volume 1 Hot-Socketing Hot-socketing, also known as hot-swapping, refers to inserting or removing a board or device into or out of a system board while system power is on. For a system to support hot-socketing, plug-in or removal of the subsystem or device must not damage the system or interrupt system operation. All devices in the Cyclone family are designed to support hot-socketing without special design requirements. The following features have been implemented in Cyclone devices to facilitate hot-socketing: Devices can be driven before power-up with no damage to the device. I/O pins remain tri-stated during power-up. Signal pins do not drive the VCCIO or VCCINT power supplies. Because 5.0-V tolerance in Cyclone devices require the use of the PCI clamping diode, and the clamping diode is only available after configuration has finished, be careful not to connect 5.0-V signals to the device. 1 Devices Can Be Driven before Power-Up The device I/O pins, dedicated input pins, and dedicated clock pins of Cyclone devices can be driven before or during power-up without damaging the devices. I/O Pins Remain Tri-Stated during Power-Up A device that does not support hot-socketing may interrupt system operation or cause contention by driving out before or during power-up. For Cyclone devices, I/O pins are tri-stated before and during power-up and configuration, and will not drive out. Signal Pins Do Not Drive the VCCIO or VCCINT Power Supplies A device that does not support hot-socketing will short power supplies together when powered-up through its signal pins. This irregular powerup can damage both the driving and driven devices and can disrupt card power-up. In Cyclone devices, there is no current path from I/O pins, dedicated input pins, or dedicated clock pins to the VCCIO or VCCINT pins before or during power-up. A Cyclone device may be inserted into (or removed from) a powered-up system board without damaging or interfering with system-board operation. When hot-socketing, Cyclone devices have a minimal effect on the signal integrity of the backplane. 11-6 Preliminary Altera Corporation May 2003 Power-Up Sequence 1 The maximum DC current when hot-socketing Cyclone devices is less than 300 A, whereas the maximum AC current during hot-socketing is less than 8 mA for a period of 10ns or less. During hot-socketing, the signal pins of a device may be connected and driven by the active system before the power supply can provide current to the device VCC and ground planes. Known as latch-up, this condition can cause parasitic diodes to turn on within the device, causing the device to consume a large amount of current, and possibly causing electrical damage. This operation can also cause parasitic diodes to turn on inside of the driven device. Cyclone devices are immune to latch-up when hotsocketing. Power-Up Sequence Because Cyclone devices can be used in a multi-voltage environment, they are designed to tolerate any possible power-up sequence. Either VCCINT or VCCIO can initially supply power to the device, and 3.3-V, 2.5-V, 1.8-V, or 1.5-V input signals can drive the devices without special precautions before VCCINT or VCCIO is applied. Cyclone devices can operate with a VCCIO voltage level that is higher than the VCCINT level. You can also change the VCCIO supply voltage while the board is powered-up. However, you must ensure that the VCCINT and VCCIO power supplies stay within the correct device operating conditions. When VCCIO and VCCINT are supplied from different power sources to a Cyclone device, a delay between VCCIO and VCCINT may occur. Normal operation does not occur until both power supplies are in their recommended operating range. When VCCINT is powered-up, the IEEE Std. 1149.1 Joint Test Action Group (JTAG) circuitry is active. If TMS and TCK are connected to VCCIO and VCCIO is not powered-up, the JTAG signals are left floating. Thus, any transition on TCK can cause the state machine to transition to an unknown JTAG state, leading to incorrect operation when VCCIO is finally powered-up. To disable the JTAG state during the power-up sequence, TCK should be pulled low to ensure that an inadvertent rising edge does not occur on TCK. Power-On Reset When designing a circuit, it is important to consider system state at power-up. Cyclone devices maintain a reset state during power-up. When power is applied to a Cyclone device, a power-on-reset event occurs if VCC reaches the recommended operating range within a certain period of time (specified as a maximum VCC rise time). A POR event does not occur if these conditions are not met because slower rise times can cause incorrect device initialization and functional failure. Altera Corporation May 2003 11-7 Preliminary Cyclone Device Handbook, Volume 1 1 If VCCINT does not remain in the specified operating range, operation is not assured until VCCINT re-enters the range. Conclusion PCBs often contain a mix of 5.0-V, 3.3-V, 2.5-V, 1.8-V, and 1.5-V devices. The Cyclone device family's MultiVolt I/O operation capability allows you to incorporate newer-generation devices with devices of varying voltage levels. This capability also enables the device core to run at its core voltage, VCCINT, while maintaining I/O pin compatibility with other logic levels. Altera has taken further steps to make system design easier by designing devices that allow VCCINT and VCCIO to power-up in any sequence and by incorporating support for hot-socketing. 11-8 Preliminary Altera Corporation May 2003 12. Designing with 1.5-V Devices C51012-1.0 Introduction The CycloneTM FPGA family provides the best solution for high-volume, cost-sensitive applications. Similar to StratixTM devices, Cyclone devices are fabricated on a leading-edge 1.5-V, 0.13-m, all-layer copper SRAM process. Using a 1.5-V operating voltage provides the following advantages: Lower power consumption compared to 2.5-V or 3.3-V devices. Lower operating temperature. Less need for fans and other temperature-control elements. Since many existing designs are based on 5.0-V, 3.3-V and 2.5-V power supplies, a voltage regulator may be required to lower the voltage supply level to 1.5-V. This application note provides guidelines for designing with Cyclone devices in mixed-voltage and single-voltage systems and provides examples using voltage regulators. This application note also includes information on: Power Sequencing & Hot Socketing Using MultiVolt I/O Pins Voltage Regulators 1.5-V Regulator Application Examples Board Layout Power Sequencing & Hot Socketing Power Sequencing & Hot Socketing Because 1.5-V Cyclone FPGAs can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. Therefore, the VCCIO and VCCINT power supplies may be powered in any order. You can drive signals into Cyclone FPGAs before and during power up without damaging the device. In addition, Cyclone FPGAs do not drive out during power up since they are tri-stated during power up. Once the device reaches operating conditions and is configured, Cyclone FPGAs operate as specified by the user. f See the Cyclone Field Programmable Gate Array Family Data Sheet for more information. Altera Corporation May 2003 12-1 Preliminary Cyclone Device Handbook, Volume 1 Using MultiVolt I/O Pins Cyclone FPGAs require a 1.5-V VCCINT and a 3.3-V, 2.5-V, 1.8-V, or 1.5-V I/O supply voltage level (VCCIO). All pins, including dedicated inputs, clock, I/O, and JTAG pins, are 3.3-V tolerant before and after VCCINT and VCCIO are powered. When VCCIO is connected to 1.5-V, the output is compatible with 1.5-V logic levels. The output pins can be made 1.8-V, 2.5-V, or 3.3-V compatible by using open-drain outputs pulled up with external resistors. You can use external resistors to pull open-drain outputs up with a 1.8-V, 2.5-V, or 3.3-V VCCIO. Table 12-1 summarizes Cyclone MultiVolt I/O support. Table 12-1. Cyclone MultiVolt I/O Support Input Signal VCCIO (V) 1.5-V 1.8-V 2.5-V 3.3-V Notes to Table 12-1: (1) (2) (3) (4) (5) (6) (7) (8) Note (1) Output Signal 3.3-V v (2) 1.5-V v 1.8-V v v 2.5-V v (2) 5.0-V 1.5-V v v (3) v (5) 1.8-V 2.5-V 3.3-V 5.0-V v v v (4) v v v v (6) v v (5) v (7) v v (7) v (7) v v (8) The PCI clamping diode must be disabled to drive an input with voltages higher than VCCIO. When VCCIO = 1.5-V and a 2.5-V or 3.3-V input signal feeds an input pin, higher pin leakage current is expected. When VCCIO = 1.8-V, a Cyclone device can drive a 1.5-V device with 1.8-V tolerant inputs. When VCCIO = 3.3-V and a 2.5-V input signal feeds an input pin, the VCCIO supply current will be slightly larger than expected. When VCCIO = 2.5-V, a Cyclone device can drive a 1.5-V or 1.8-V device with 2.5-V tolerant inputs. Cyclone devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode. When VCCIO = 3.3-V, a Cyclone device can drive a 1.5-V, 1.8-V, or 2.5-V device with 3.3-V tolerant inputs. When VCCIO = 3.3-V, a Cyclone device can drive a device with 5.0-V LVTTL inputs but not 5.0-V LVCMOS inputs. Figure 12-1 shows how Cyclone FPGAs interface with 3.3--V and 2.5-V devices while operating with a 1.5-V VCCINT to increase performance and save power. 12-2 Preliminary Altera Corporation May 2003 Voltage Regulators Figure 12-1. Cyclone FPGAs Interface with 3.3-V & 2.5-V Devices 3.3 V 2.5 V 1.5 V Cyclone Device 3.3-V TTL 3.3-V Device 3.3-V CMOS VCCINT = 1.5 V VCCIO1 = 2.5 V VCCIO2 = 3.3 V 2.5-V TTL 2.5-V Device 2.5-V CMOS Voltage Regulators This section explains how to generate a 1.5-V supply from another system supply. Supplying power to the 1.5-V logic array and/or I/O pins requires a 5.0-V- or 3.3-V-to-1.5-V voltage regulator. A linear regulator is ideal for low-power applications because it minimizes device count and has acceptable efficiency for most applications. A switching voltage regulator provides optimal efficiency. Switching regulators are ideal for high-power applications because of their high efficiency. This section will help you decide which regulator to use in your system, and how to implement the regulator in your design. There are several companies that provide voltage regulators for low-voltage devices, such as Linear Technology Corporation, Maxim Integrated Products, Intersil Corporation (Elantec), and National Semiconductor Corporation. Table 12-2 shows the terminology and specifications commonly encountered with voltage regulators. Symbols are shown in parentheses. If the symbols are different for linear and switching regulators, the linear regulator symbol is listed first. Table 12-2. Voltage Regulator Specifications & Terminology (Part 1 of 2) Specification/Terminology Input voltage range (VIN,VCC) Line regulation (line regulation, VOUT) Description Minimum and maximum input voltages define the input voltage range, which is determined by the regulator process voltage capabilities. Line regulation is the variation of the output voltage (VOUT) with changes in the input voltage (VIN). Error amplifier gain, pass transistor gain, and output impedance all influence line regulation. Higher gain results in better regulation. Board layout and regulator pin-outs are also important because stray resistance can introduce errors. Altera Corporation May 2003 12-3 Preliminary Cyclone Device Handbook, Volume 1 Table 12-2. Voltage Regulator Specifications & Terminology (Part 2 of 2) Specification/Terminology Load regulation (load regulation, VOUT) Description Load regulation is a variation in the output voltage caused by changes in the input supply current. Linear Technology regulators are designed to minimize load regulation, which is affected by error amplifier gain, pass transistor gain, and output impedance. Output voltage selection is adjustable by resistor voltage divider networks, connected to the error amplifier input, that control the output voltage. There are multiple output regulators that create 5.0-, 3.3-, 2.5-, 1.8- and 1.5-V supplies. Quiescent current is the supply current during no-load or quiescent state. This current is sometimes used as a general term for a supply current used by the regulator. Dropout voltage is the difference between the input and output voltages when the input is low enough to cause the output to drop out of regulation. The dropout voltage should be as low as possible for better efficiency. Voltage regulators are designed to limit the amount of output current in the event of a failing load. A short in the load causes the output current and voltage to decrease. This event cuts power dissipation in the regulator during a short circuit. This feature limits power dissipation if the regulator overheats. When a specified temperature is reached, the regulator turns off the output drive transistors, allowing the regulator to cool. Normal operation resumes once the regulator reaches a normal operating temperature. If the input power supply fails, large output capacitors can cause a substantial reverse current to flow backward through the regulator, potentially causing damage. To prevent damage, protection diodes in the regulator create a path for the current to flow from VOUT to VIN. The dominant pole placed by the output capacitor influences stability. Voltage regulator vendors can assist you in output capacitor selection for regulator designs that differ from what is offered. A minimum load from the voltage divider network is required for good regulation, which also serves as the ground for the regulator's current path. Efficiency is the division of the output power by the input power. Each regulator model has a specific efficiency value. The higher the efficiency value, the better the regulator. Output voltage selection Quiescent current Dropout voltage Current limiting Thermal overload protection Reverse current protection Stability Minimum load requirements Efficiency Linear Voltage Regulators Linear voltage regulators generate a regulated output from a larger input voltage using current pass elements in a linear mode. There are two types of linear regulators available: one using a series pass element and another using a shunt element (e.g., a zener diode). Altera recommends using series linear regulators because shunt regulators are less efficient. 12-4 Preliminary Altera Corporation May 2003 Voltage Regulators Series linear regulators use a series pass element (i.e., a bipolar transistor or MOSFET) controlled by a feedback error amplifier (see Figure 12-2) to regulate the output voltage by comparing the output to a reference voltage. The error amplifier drives the transistor further on or off continuously to control the flow of current needed to sustain a steady voltage level across the load. Figure 12-2. Series Linear Regulator VIN VOUT Error Amplifier + - Reference Table 12-3 shows the advantages and disadvantages of linear regulators compared to switching regulators. Table 12-3. Linear Regulator Advantages & Disadvantages Advantages Requires few supporting components Low cost Requires less board space Quick transient response Better noise and drift characteristics No electromagnetic interference (EMI) radiation from the switching components Tighter regulation Disadvantages Less efficient (typically 60%) Higher power dissipation Larger heat sink requirements You can minimize the difference between the input and output voltages to improve the efficiency of linear regulators. The dropout voltage is the minimum allowable difference between the regulator's input and output voltage. Altera Corporation May 2003 12-5 Preliminary Cyclone Device Handbook, Volume 1 Linear regulators are available with fixed, variable, single, or multiple outputs. Multiple-output regulators can generate multiple outputs (e.g., 1.5- and 3.3-V outputs). If the board only has a 5.0-V power voltage supply, you should use multiple-output regulators. The logic array requires a 1.5-V power supply, and a 3.3-V power supply is required to interface with 3.3- and 5.0-V devices. However, fixed-output regulators have fewer supporting components, reducing board space and cost. Figure 12-3 shows an example of a three-terminal, fixed-output linear regulator. Figure 12-3. Three-Terminal, Fixed-Output Linear Regulator Linear Regulator VIN IN ADJ OUT 1.5 V Adjustable-output regulators contain a voltage divider network that controls the regulator's output. Figure 12-4 shows how you can also use a three-terminal linear regulator in an adjustable-output configuration. Figure 12-4. Adjustable-Output Linear Regulator Linear Regulator VIN + C1 IADJ R2 IN ADJ OUT VREF R1 + C2 VOUT = [VREF x (1 + R1 R2 )] + (IADJ x R1) Switching Voltage Regulators Step-down switching regulators can provide 3.3-V-to-1.5-V conversion with up to 95% efficiencies. This high efficiency comes from minimizing quiescent current, using a low-resistance power MOSFET switch, and, in higher-current applications, using a synchronous switch to reduce diode losses. 12-6 Preliminary Altera Corporation May 2003 Voltage Regulators Switching regulators supply power by pulsing the output voltage and current to the load. Table 12-4 shows the advantages and disadvantages of switching regulators compared to linear regulators. For more information on switching regulators, see Application Note 35: Step Down Switching Regulators from Linear Technology. Table 12-4. Switching Regulator Advantages & Disadvantages Advantages Highly efficient (typically >80%) Reduced power dissipation Smaller heat sink requirements Wider input voltage range High power density Disadvantages Generates EMI Complex to design Requires 15 or more supporting components Higher cost Requires more board space There are two types of switching regulators, asynchronous and synchronous. Asynchronous switching regulators have one field effect transistor (FET) and a diode to provide the current path while the FET is off (see Figure 12-5). Figure 12-5. Asynchronous Switching Regulator MOSFET VIN Switch Node VOUT High-Frequency Circulating Path LOAD Synchronous switching regulators have a voltage- or current-controlled oscillator that controls the on and off time of the two MOSFET devices that supply the current to the circuit (see Figure 12-6). Altera Corporation May 2003 12-7 Preliminary Cyclone Device Handbook, Volume 1 Figure 12-6. Voltage-Controlled Synchronous Switching Regulator VIN Voltage-Controlled Oscillator (VCO) VOUT Maximum Output Current Select an external MOSFET switching transistor (optional) based on the maximum output current that it can supply. Use a MOSFET with a low on-resistance and a voltage rating high enough to avoid avalanche breakdown. For gate-drive voltages less than 9-V, use a logic-level MOSFET. A logic-level MOSFET is only required for topologies with a controller IC and an external MOSFET. Selecting Voltage Regulators Your design requirements determine which voltage regulator you need. The key to selecting a voltage regulator is understanding the regulator parameters and how they relate to the design. The following checklist can help you select the proper regulator for your design: Do you require a 3.3-V, 2.5-V, and 1.5-V output (VOUT)? What precision is required on the regulated 1.5-V supplies (line and load regulation)? What supply voltages (VIN or VCC) are available on the board? What voltage variance (input voltage range) is expected on VIN or VCC? What is the maximum ICC (IOUT) required by your Altera(R) device? What is the maximum current surge (IOUT(MAX)) that the regulator will need to supply instantaneously? 12-8 Preliminary Altera Corporation May 2003 Voltage Regulators Choose a Regulator Type If required, select either a linear, asynchronous switching, or synchronous switching regulator based on your output current, regulator efficiency, cost, and board-space requirements. DC-to-DC converters have output current capabilities from 1 to 8 A. You can use a controller with an external MOSFET rated for higher current for higher-outputcurrent applications. Calculate the Maximum Input Current Use the following equation to estimate the maximum input current based on the output power requirements at the maximum input voltage: VOUT x IOUT(MAX) x VIN(MAX) IIN,DC(MAX) = Where is nominal efficiency: typically 90% for switching regulators, 60% for linear 2.5-V-to-1.5-V conversion, 45% for linear 3.3-V-to-1.5-V conversion, and 30% for linear 5.0-V-to-1.5-V conversion. Once you identify the design requirements, select the voltage regulator that is best for your design. Tables 12-5 and 12-6 list a few Linear Technology and Elantec regulators available at the time this document was published. There may be more regulators to choose from depending on your design specification. Contact a regulator manufacturer for availability. Table 12-5. Linear Technology 1.5-V Output Voltage Regulators Voltage Regulator LT1573 LT1083 LT1084 LT1085 LTC1649 LTC1775 Note to Table 12-5: (1) A 3.3-V VIN requires a 3.3-V supply to the regulator's input and 2.5-V supply to bias the transistors. Regulator Type Linear Linear Linear Linear Switching Switching Total Number of Components 10 5 5 5 22 17 5.0 5.0 5.0 3.3 5.0 VIN (V) 2.5 or 3.3 (1) 6 IOUT (A) - - - Special Features 7.5 5 3 15 5 Inexpensive solution Selectable output - Altera Corporation May 2003 12-9 Preliminary Cyclone Device Handbook, Volume 1 Table 12-6. Elantec 1.5-V Output Voltage Regulators Voltage Regulator EL7551C EL7564CM EL7556BC EL7562CM EL7563CM Regulator Type Switching Switching Switching Switching Switching Total Number of Components 11 13 21 17 19 5.0 5.0 5.0 VIN (V) 1 4 6 2 4 IOUT (A) - - - - - Special Features 3.3 or 5.5 3.3 Voltage Divider Network Design a voltage divider network if you are using an adjustable output regulator. Follow the controller or converter IC's instructions to adjust the output voltage. 1.5-V Regulator Circuits This section contains the circuit diagrams for the voltage regulators discussed in this application note. You can use the voltage regulators in this section to generate a 1.5-V power supply. Refer to the voltage regulator data sheet to find detailed specifications. If you require further information that is not shown in the data sheet, contact the regulator's vendor. Figures 12-7 through 12-12 show the circuit diagrams of Linear Technology voltage regulators listed in Table 12-5. The LT1573 linear voltage regulator converts 2.5-V to 1.5-V with an output current of 6A (see Figure 12-7). 12-10 Preliminary Altera Corporation May 2003 Voltage Regulators Figure 12-7. LT1573: 2.5-V-to-1.5-V/6.0-A Linear Voltage Regulator LT1573 FB LATCH CTIME 0.5 F (3) + SHDN (2) GND COMP VOUT VIN RD 6 1/2 W RB 200 1/8 W CIN1 + VIN1 2.5 V (1) DRIVE Motorola D45H11 VOUT 1.5 V LOAD VIN2 3.3 V + CIN2 + COUT R1 186 1/8 W R2 1k 1/8 W (4) (1) Notes to Figure 12-7: (1) (2) (3) (4) CIN1 and COUT are AVX 100-F/10-V surface-mount tantalum capacitors. Use SHDN (active high) to shut down the regulator. CTIME is a 0.5-F capacitor for 100-ms time out at room temperature. CIN2 is an AVX 15-F/10-V surface-mount tantalum capacitor. Use adjustable 5.0- to 1.5-V regulators (shown in Figures 12-8 through 12-10) for 3.0- to 7.5-A low-cost, low-device-count, board-space-efficient solutions. Figure 12-8. LT1083: 5.0-V-to-1.5-V/7.5-A Linear Voltage Regulator VIN IN LT1083 ADJ OUT R1 5 k C2 + VOUT = 1.25 V x (1 + R2 R1 ) (1) C1 + 10 F R2 1 k 10 F Note to Figure 12-8: (1) This capacitor is necessary to maintain the voltage level at the input regulator. There could be a voltage drop at the input if the voltage supply is too far away. Altera Corporation May 2003 12-11 Preliminary Cyclone Device Handbook, Volume 1 Figure 12-9. LT1084: 5.0-V-to-1.5-V/5.0-A Linear Voltage Regulator VIN IN LT1083 ADJ OUT R1 5 k C2 + VOUT = 1.25 V x (1 + R2 R1 ) (1) C1 + 10 F R2 1 k 10 F Note to Figure 12-9: (1) This capacitor is necessary to maintain the voltage level at the input regulator. There could be a voltage drop at the input if the voltage supply is too far away. Figure 12-10. LT1085: 5.0-V-to-1.5-V/3-A Linear Voltage Regulator VIN IN LT1084 ADJ OUT R1 5 k C2 + VOUT = 1.25 V x (1 + R2 R1 ) (1) C1 + 10 F R2 1 k 10 F Note to Figure 12-10: (1) This capacitor is necessary to maintain the voltage level at the input regulator. There could be a voltage drop at the input if the voltage supply is too far away. 12-12 Preliminary Altera Corporation May 2003 Voltage Regulators Figure 12-11 shows a high-efficiency switching regulator circuit diagram. A selectable resistor network controls the output voltage. The resistor values in Figure 12-11 are selected for 1.5-V output operation. Figure 12-11. LT1649: 3.3-V-to-1.5-V/15-A Asynchronous Switching Regulator VIN 3.3 V MBR0530 (1) RIMAX 50 k Q1, Q2 IRF7801 Two in Parallel (2) + CIN 3,300 F LEXT (3) 1.2 H VOUT R1 2.16 k 1.5 V (15 A) 1 F 22 k P VCC1 P VCC2 V CC I MAX LTC1649 G1 1 k I FB G2 FB V IN C+ C- CP OUT Q3 IRF7801 SHUTDOWN SHDN 10 F + COMP SS GND + 1 F R2 12.7 k COUT 4,400 F RC 7.5 k 0.1 F MBR0530 10 F + 0.33 F C1 220 pF CC 0.01 F Notes to Figure 12-11: (1) (2) (3) MBR0530 is a Motorola device. IRF7801 is a International Rectifier device. Refer to the Panasonic 12TS-1R2HL device. Altera Corporation May 2003 12-13 Preliminary Cyclone Device Handbook, Volume 1 Figure 12-12 shows synchronous switching regulator with adjustable outputs. Figure 12-12. LTC1775: 5.0-V-to-1.5-V/5-A Synchronous Switching Regulator RF 1 1 2 CSS 0.1 F EXTVCC SYNC VIN TK 16 15 CF 0.1 F VIN 5V CIN (1) 15 F 35 V x3 M1 1/2 FDS8936A L1 (2) 6.1 H VOUT 1.5 V 5A R2 2.6 k COUT (3) 680 F 4V x2 3 INTVCC 4 5 CC2 220 pF RUN/SS FCB ITH SW TG BOOST 14 13 12 CB 0.22 F DB CMDSH-3 CC1 2.2 nF RC 10 k 6 SGND INTVCC 11 D1 MBRS140 7 8 VOSENSE VPROG BG PGND 10 9 CVCC 4.7 F M2 1/2 FDS8936A R1 10 k OPEN Notes to Figure 12-12: (1) (2) (3) This is a KEMETT495X156M035AS capacitor. This is a Sumida CDRH127-6R1 inductor. This is a KEMETT510X687K004AS capacitor. 12-14 Preliminary Altera Corporation May 2003 Voltage Regulators Figures 12-13 through 12-17 show the circuit diagrams of Elantec voltage regulators listed in Table 12-6. Figures 12-13 through 12-15 show the switching regulator that converts 5.0-V to 1.5-V with different output current. Figure 12-13. EL7551C: 5.0-V-to-1.5-V/1-A Synchronous Switching Regulator 1 C3 0.1 F R3 39 k C4 270 pF SGND PGND 16 C5 0.1 F R2 539 R1 1 k 2 COSC 3 VDD 4 PGND PGND FB VDRV LX VREF 15 14 13 12 C1 10 F Ceramic 5 L1 10 H V0 1.5 V 1A 6 7 VIN 5.0 V VIN VIN LX VHI 11 10 9 C6 0.1 F C7 47 F 8 EN EL7551C PGND Altera Corporation May 2003 12-15 Preliminary Cyclone Device Handbook, Volume 1 Figure 12-14. EL7564CM: 5.0-V-to-1.5-V/4-A Synchronous Switching Regulator 1 VREF C5 0.1 F 2 SGND 3 C4 390 pF 4 C3 0.22 F C2 2.2 nF 5 VDD VTJ VDRV VHI COSC FB PG EN 20 19 18 R4 22 17 16 C6 0.22 F D1 6 PGND 7 PGND C1 330 F VIN 5.0 V LX LX 15 14 L1 4.7 H V0 1.5 V 4A C7 330 F 13 12 11 R2 539 C10 100 pF 8 9 10 VIN STP STN EL7564CM PGND PGND PGND R1 1 k 12-16 Preliminary Altera Corporation May 2003 Voltage Regulators Figure 12-15. EL7556BC: 5.0-V-to-1.5-V/6-A Synchronous Switching Regulator R4 100 R3 50 VIN C4 (1) 0.1 F C7 (1) 39 pF C8 (1) 220 pF R5 5.1 1 2 FB1 CREF FB2 CP 28 27 C5 (2) 1 F R1 20 D3 (3) D4 Optional (3), (4) D2 (3) C11 (2) 0.22 F 3 CSLOPE COSC C2V VSS 26 4 25 D1 (3) R6 39.2 C6 (1) 0.1 F L1 2.5 H 5 6 7 8 VDD VIN VSSP VIN VSSP VSSP VSSP VSSP VCC2DET OUTEN EL7556BC VHI LX LX LX LX VSSP VSSP 24 23 22 21 20 19 18 VIN C9 (5) 660 F C12 1.0 F 9 10 11 VOUT R3 = 1.5 V x (1 + ) R4 12 13 14 TEST 17 16 PWRGD 15 OT C10 (6) 1.0 mF Notes to Figures 12-13 - 12-15: (1) (2) (3) (4) (5) (6) These capacitors are ceramic capacitors. These capacitors are ceramic or tantalum capacitor. These are BAT54S fast diodes. D4 is only required for EL7556ACM. This is a Sprague 293D337X96R3 2X330F capacitor. This is a Sprague 293D337X96R3 3X330F capacitor. Altera Corporation May 2003 12-17 Preliminary Cyclone Device Handbook, Volume 1 Figures 12-16 and 12-17 show the switching regulator that converts 3.3 V to 1.5 V with different output currents. Figure 12-16. EL7562CM: 3.3-V to 1.5-V/2-A Synchronous Switching Regulator 1 C4 270 pF SGND PGND 16 C5 0.1 F C3 R3 0.1 F 39 2 3 COSC VDD PGND VREF FB 15 14 D2 4 VDRV 13 D3 D4 5 C1 100 F VIN 3.3 V C2 0.1 F 6 7 8 PGND VIN VIN EN LX LX VHI PGND 12 11 10 9 C8 0.1 F C6 0.1 F C9 0.1 F L1 2.5 H VOUT 1.5 V 2A C7 100 F R2 539 R1 1 k EL7562CM Figure 12-17. EL7563CM: 3.3-V to 1.5-V/4-A Synchronous Switching Regulator C5 0.1 F 1 2 C4 390 pF 3 R4 22 C3 0.22 F C2 2.2 nF 5 COSC VDD PG 18 D2 D4 VREF SGND EN FB 20 19 4 VDRV 17 D3 C9 0.1 F VTJ VHI 16 C6 0.22 F C8 0.22 F D1 L1 2.5 H 6 C1 330 F VIN 3.3 V 7 8 9 10 PGND PGND VIN STP STN LX LX PGND PGND PGND 15 14 13 12 11 R1 1 k C7 330 F C10 2.2 nF R2 513 VOUT 1.5 V 4A EL7563CM 12-18 Preliminary Altera Corporation May 2003 1.5-V Regulator Application Examples 1.5-V Regulator Application Examples The following sections show the process used to select a voltage regulator for three sample designs. The regulator selection is based on the amount of power that the Cyclone device consumes. There are 14 variables to consider when selecting a voltage regulator. The following variables apply to Cyclone device power consumption: fMAX Output and bidirectional pins Average toggle rate for I/O pins (togIO) Average toggle rate for logic elements (LEs) (togLC) User-mode ICC consumption Maximum power-up ICCINT requirement Utilization VCCIO supply level VCCINT supply level The following variables apply to the voltage regulator: Output voltage precision requirement Supply voltage on the board Voltage supply output current Variance of board supply Efficiency Different designs have different power consumptions based on the variables listed. Once you calculate the Cyclone device's power consumption, you must consider how much current the Cyclone device needs. You can use the Cyclone power calculator (available at www.altera.com) or the PowerGaugeTM tool in the Quartus II software to determine the current needs. Also check the maximum power-up current requirement listed in the Power Consumption section of the Cyclone FPGA Family Data Sheet because the power-up current requirement may exceed the user-mode current consumption for a specific design. Once you determine the minimum current the Cyclone device requires, you must select a voltage regulator that can generate the desired output current with the voltage and current supply that is available on the board using the variables listed in this section. An example is shown to illustrate the voltage regulator selection process. Altera Corporation May 2003 12-19 Preliminary Cyclone Device Handbook, Volume 1 Synchronous Switching Regulator Example This example shows a worst-case scenario for power consumption where the design uses all the LEs and RAM. Table 12-7 shows the design requirements for 1.5-V design using a Cyclone EP1C12 FPGA. Table 12-7. Design Requirements for the Example EP1C12F324C Design Requirement Output voltage precision requirement Supply voltages available on the board Voltage supply output current available for this section (II N , D C ( M A X ) ) Variance of board supply (VIN) fMAX Average togIO Average togLC Utilization Output and bidirectional pins VCCIO supply level VCCINT supply level Efficiency 5% 3.3 V 2A 5% 150 MHz 12.5% 12.5% 100% 125 3.3 V 1.5 V 90% Value Table 12-8 uses the checklist on page 12-8 to help select the appropriate voltage regulator. Table 12-8. Voltage Regulator Selection Process for EP1C12F324C Design (Part 1 of 2) Output voltage requirements Supply voltages Supply variance from Linear Technology data sheet Estimated IC C I N T Use Cyclone Power Calculator Estimated IC C I O if regulator powers VC C I O Use Cyclone Power Calculator (not applicable in this example because VC C I O = 3.3 V) Total user-mode current consumption IC C = I C C I N T + I C C I O VOUT = 1.5 V VIN OR VCC = 3.3 V Supply variance = 5% ICCINT = 620 mA ICCIO = N/A IC C = 620 mA 12-20 Preliminary Altera Corporation May 2003 Board Layout Table 12-8. Voltage Regulator Selection Process for EP1C12F324C Design (Part 2 of 2) EP1C12 maximum power-up current requirement See Power Consumption section of the Cyclone FPGA Family Data Sheet for other densities Maximum output current required Compare IC C with IP U C ( M A X ) Voltage regulator selection See Linear Technology LTC 1649 data sheet See Intersil (Elantec) EL7562C data sheet IP U C ( M A X ) = 900 mA IO U T ( M A X ) = 900 mA LTC1649 IO U T ( M A X ) = 15 A EL7562C IO U T ( M A X ) = 2 A LTC1649 Nominal efficiency ( ) Line and load regulation Line regulation + load regulation = (0.17 mV + 7 mV)/ 1.5 V x 100% Minimum input voltage (VIN(MIN)) (VIN(MIN)) = VIN(1 - VIN) = 3.3V(1 - 0.05) Maximum input current IIN, DC(MAX) = (VOUT x IOUT(MAX))/( x VIN(MIN)) Nominal efficiency ( ) = > 90% Line and Load Regulation = 0.478% < 5% (VIN(MIN)) = 3.135 V IIN, DC(MAX) = 478 mA < 2 A EL7562C Nominal efficiency ( ) Line and load regulation Line regulation + load regulation = (0.17 mV + 7 mV)/ 1.5 V x 100% Minimum input voltage (VIN(MIN)) (VIN(MIN)) = VIN(1 - VIN) = 3.3V(1 - 0.05) Maximum input current IIN, DC(MAX) = (VOUT x IOUT(MAX))/( x VIN(MIN)) Nominal efficiency ( ) = > 95% Line and Load Regulation = 0.5% < 5% (VIN(MIN)) = 3.135 V IIN, DC(MAX) = 453 mA < 2 A Board Layout Laying out a printed circuit board (PCB) properly is extremely important in high-frequency (100 kHz) switching regulator designs. A poor PCB layout results in increased EMI and ground bounce, which affects the reliability of the voltage regulator by obscuring important voltage and current feedback signals. Altera recommends using Gerber files predesigned layout files supplied by the regulator vendor for your board layout. If you cannot use the supplied layout files, contact the voltage regulator vendor for help on re-designing the board to fit your design requirements while maintaining the proper functionality. Altera recommends that you use separate layers for signals, the ground plane, and voltage supply planes. You can support separate layers by using multi-layer PCBs, assuming you are using two signal layers. Altera Corporation May 2003 12-21 Preliminary Cyclone Device Handbook, Volume 1 Figure 12-18 shows how to use regulators to generate 1.5-V and 2.5-V power supplies if the system needs two power supply systems. One regulator is used for each power supply. Figure 12-18. Two Regulator Solution for Systems that Require 5.0-V, 2.5-V & 1.5-V Supply Levels PCB 5.0 V Regulator 1.5 V 1.5-V Device Altera Cyclone FPGA Regulator 2.5 V 2.5-V Device Figure 12-19 shows how to use a single regulator to generate two different power supplies (1.5-V and 2.5-V). The use of a single regulator to generate 1.5-V and 2.5-V supplies from the 5.0-V power supply can minimize the board size and thus save cost. Figure 12-19. Single Regulator Solution for Systems that Require 5.0-V, 2.5-V & 1.5-V Supply Levels PCB 1.5-V Device 1.5 V 5.0 V Regulator 2.5 V Altera Cyclone FPGA 2.5-V Device 12-22 Preliminary Altera Corporation May 2003 Conclusion Split-Plane Method The split-plane design method reduces the number of planes required by placing two power supply planes in one plane (see Figure 12-20). For example, the layout for this method can be structured as follows: One 2.5-V plane, covering the entire board One plane split between 5.0-V and 1.5-V This technique assumes that the majority of devices are 2.5-V. To support MultiVolt I/O, Altera devices must have access to 1.5-V and 2.5-V planes. Figure 12-20. Split Board Layout for 2.5-V Systems With 5.0-V & 1.5-V Devices PCB 5.0 V 1.5 V 2.5-V Device 5.0-V Device 1.5-V Device 5.0-V Device Regulator Altera Cyclone FPGA (1.5 V) 2.5-V Device 2.5-V Device 1.5-V Device 2.5-V Device Conclusion With the proliferation of multiple voltage levels in systems, it is important to design a voltage system that can support a low-power device like Cyclone devices. Designers must consider key elements of the PCB, such as power supplies, regulators, power consumption, and board layout when successfully designing a system that incorporates the lowvoltage Cyclone family of devices. Altera Corporation May 2003 12-23 Preliminary Cyclone Device Handbook, Volume 1 References Linear Technology Corporation. Application Note 35 (Step-Down Switching Regulators). Milpitas: Linear Technology Corporation, 1989. Linear Technology Corporation. LT1573 Data Sheet (Low Dropout Regulator Driver). Milpitas: Linear Technology Corporation, 1997. Linear Technology Corporation. LT1083/LT1084/LT1085 Data Sheet (7.5 A, 5 A, 3 A Low Dropout Positive Adjustable Regulators). Milpitas: Linear Technology Corporation, 1994. Linear Technology Corporation. LTC1649 Data Sheet (3.3V Input High Power Step-Down Switching Regulator Controller). Milpitas: Linear Technology Corporation, 1998. Linear Technology Corporation. LTC1775 Data Sheet (High Power No Rsense Current Mode Synchronous Step-Down Switching Regulator). Milpitas: Linear Technology Corporation, 1999. Intersil Corporation. EL7551C Data Sheet (Monolithic 1 Amp DC:DC StepDown Regulator). Milpitas: Intersil Corporation, 2002. Intersil Corporation. EL7564C Data Sheet (Monolithic 4 Amp DC:DC StepDown Regulator). Milpitas: Intersil Corporation, 2002. Intersil Corporation. EL7556BC Data Sheet (Integrated Adjustable 6 Amp Synchronous Switcher). Milpitas: Intersil Corporation, 2001. Intersil Corporation. EL7562C ta Sheet (Monolithic 2 Amp DC:DC StepDown Regulator). Milpitas: Intersil Corporation, 2002. Intersil Corporation. EL7563C Data Sheet (Monolithic 4 Amp DC:DC StepDown Regulator). Milpitas: Intersil Corporation, 2002. 12-24 Preliminary Altera Corporation May 2003 Section VI. Configuration This section provides information for all of the supported configuration schemes for Cyclone devices. The last chapter provides information on EPCS1 and EPCS4 serial configuration devices. This section contains the following chapters: Chapter 13. Configuring Cyclone FPGAs Chapter 14. Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet Revision History The table below shows the revision history for Chapter 13 and 14. Chapter(s) 13 Date / Version May 2003 v1.0 Changes Made Updates to existing figures and notes. Added Figure 13-2 and Figure 13-3. Added information for EP1C4 and removed EPC1441. Initial release. 14 May 2003 v1.0 Altera Corporation Section VI-1 Preliminary Configuration Cyclone Device Handbook, Volume 1 Section VI-2 Preliminary Altera Corporation 13. Configuring Cyclone FPGAs C51013-1.0 Introduction You can configure CycloneTM FPGAs using one of several configuration schemes, including the new active serial (AS) configuration scheme. This new scheme is used with the new, low cost serial configuration devices. Passive serial (PS) and Joint Test Action Group (JTAG)-based configuration schemes are also supported by Cyclone FPGAs. Additionally, Cyclone FPGAs can receive a compressed configuration bit stream and decompress this data in real-time, reducing storage requirements and configuration time. This application note provides details on each of the three supported Cyclone configuration schemes. Device Configuration Overview Cyclone FPGAs use SRAM cells to store configuration data. Since SRAM memory is volatile, configuration data must be downloaded to Cyclone FPGAs each time the device powers up. You can download configuration data to Cyclone FPGAs using the AS, PS, or JTAG interfaces. See Table 13-1. Table 13-1. Cyclone FPGA Configuration Schemes Configuration Scheme Description Active serial (AS) configuration Configuration using: Serial configuration devices (EPCS1 or EPCS4) Passive serial (PS) configuration Configuration using: Enhanced configuration devices (EPC4, EPC8, and EPC16) EPC2, EPC1 configuration devices Intelligent host (microprocessor) Download cable JTAG-based configuration Configuration via JTAG pins using: Download cable Intelligent host (microprocessor) JamTM Standard Test and Programming Language (STAPL) Altera Corporation May 2003 13-1 Preliminary Cyclone Device Handbook, Volume 1 You can select a Cyclone FPGA configuration scheme by driving its MSEL1 and MSEL0 pins either high (1) or low (0), as shown in Table 13-2. Table 13-2. Selecting Cyclone Configuration Schemes MSEL1 0 0 0 Notes to Table 13-2: (1) (2) (3) You can set MSEL0 either high or low. Do not leave MSEL pins floating. Connect them to a low- or high-logic level. JTAG-based configuration takes precedence over other schemes (i.e., ignores MSEL pin settings). MSEL0 0 1 (1) Configuration Scheme AS PS JTAG-based (2), (3) After configuration, Cyclone FPGAs will initialize registers and I/O pins, then enter user mode and function as per the user design. Figure 13-1 shows an AS configuration waveform. Figure 13-1. AS Configuration Waveform nCONFIG nSTATUS CONF_DONE nCSO DCLK ASDO Read Address DATA0 bit N bit N - 1 bit 1 bit 0 136 Cycles INIT_DONE User I/O User Mode You can configure Cyclone FPGAs using the 3.3-V, 2.5-V, 1.8-V, or 1.5-V LVTTL I/O standard on configuration and JTAG input pins. These devices do not feature a VCCSEL pin; therefore, you should connect the VCCIO pins of the I/O banks containing configuration or JTAG pins according to the I/O standard specifications. 13-2 Preliminary Altera Corporation May 2003 Data Compression Table 13-3 summarizes the approximate uncompressed configuration file size for each Cyclone FPGA. To calculate the amount of storage space required for multi-device configurations, add the file size of each device together. Table 13-3. Cyclone Configuration File Sizes Device EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 Note to Table 13-3: (1) These values are preliminary. Note (1) SRAM Object File Size (Mbits) 0.628 0.925 1.167 2.324 3.559 You should only use the numbers in Table 13-3 to estimate the SRAM Object File (.sof) size before design compilation. The exact file size can vary because different Altera(R) Quartus(R) II software versions can add a slightly different number of padding bits during programming. However, for any specific version of the Quartus II software, any design targeted for the same device has the same uncompressed configuration file size. If compression is used, the file size can vary after each compilation. Data Compression Cyclone FPGAs are the first FPGAs to support decompression of configuration data. This feature allows you to store compressed configuration data in configuration devices or other memory, and transmit this compressed bit stream to Cyclone FPGAs. During configuration, the Cyclone FPGA decompresses the bit stream in real time and programs its SRAM cells. Cyclone FPGAs support compression in the AS and PS configuration schemes. Compression is not supported for JTAG-based configuration. 1 Preliminary data indicates that compression reduces configuration bit stream size by 35 to 60%. When you enable compression, the Quartus II software generates configuration files with compressed configuration data. This compression reduces the storage requirements in the configuration device or flash, and decreases the time needed to transmit the bit stream to the Cyclone FPGA. Altera Corporation May 2003 13-3 Preliminary Cyclone Device Handbook, Volume 1 There are two methods to enable compression for Cyclone bitstreams: before design compilation (in Compiler Settings menu) & after design compilation (in Convert Programming Files window). To enable compression in the project's compiler settings, select "Device" under the "Assignments" menu to bring up the settings window. After selecting your Cyclone device open the "Device & Pin Options" window, and in the "General" settings tab enable the check box for "Generate compressed bitstreams" (as shown in Figure 13-2). Figure 13-2. Enabling compression for Cyclone bitstreams in Compiler Settings Compression can also be enabled when creating programming files from the "Convert Programming Files". See Figure 13-3. 1. 2. Open "File -> Convert Programming Files". Select the Programming File type (POF, SRAM HEXOUT, RBF, or TTF). For POF output files, select a configuration device. Select "Add File" and add Cyclone SOF file. 3. 4. 13-4 Preliminary Altera Corporation May 2003 Data Compression 5. Select the name of file you added to the "SOF Data" area and click on "Properties". Enable the "Compression" checkbox. 6. Figure 13-3. Enabling compression for Cyclone bitstreams in Convert Programming Files When multiple Cyclone devices are cascaded, the compression feature can be selectively enabled for each device in the chain. Figure 13-4 depicts a chain of two Cyclone FPGAs. The first Cyclone FPGA has compression enabled and therefore receives a compressed bit stream from the configuration device. The second Cyclone FPGA has the compression feature disabled and receives uncompressed data. Altera Corporation May 2003 13-5 Preliminary Cyclone Device Handbook, Volume 1 Figure 13-4. Compressed & Uncompressed Configuration Data in the Same Programming File Serial Data Serial or Enhanced Configuration Device Compressed Uncompressed Note (1) Decompression Controller Decompression Controller Cyclone FPGA nCE GND nCEO Cyclone FPGA nCE nCEO Note to Figure 13-4: (1) The first device in the chain should be set up in AS configuration mode (MSEL[1..0]="00"). The remaining devices in the chain must be set up in PS configuration mode (MSEL[1..0]="01"). You can generate programming files for this setup from the Convert Programming Files window (File menu) in the Quartus II software. The decompression feature supported by Cyclone FPGAs is separate from the decompression feature in enhanced configuration devices (EPC16, EPC8, and EPC4). The data compression feature in the enhanced configuration devices allows them to store compressed data and decompress the bit stream before transmitting to the target devices. When using Cyclone FPGAs with enhanced configuration devices, Altera recommends using compression on one of the devices, not both (preferably the Cyclone FPGA since transmitting compressed data reduces configuration time). Configuration Schemes This section describes the various configuration schemes you can use to configure Cyclone FPGAs. Descriptions include an overview of the protocol, pin connections, and timing information. The schemes discussed are: AS configuration (serial configuration devices) PS configuration JTAG-based configuration 13-6 Preliminary Altera Corporation May 2003 Configuration Schemes Active Serial Configuration (Serial Configuration Devices) In the AS configuration scheme, Cyclone FPGAs are configured using the new serial configuration devices. These configuration devices are low cost devices with non-volatile memory that feature a simple four-pin interface and a small form factor. These features make serial configuration devices an ideal solution for configuring the low-cost Cyclone FPGAs. f For more information on serial configuration devices, see Chapter 14, Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet. Serial configuration devices provide a serial interface to access configuration data. During device configuration, Cyclone FPGAs read configuration data via the serial interface, decompress data if necessary, and program their SRAM cells. This scheme is referred to as an AS configuration scheme because the FPGA controls the configuration interface. This scheme is in contrast to the PS configuration scheme where the configuration device controls the interface. Serial configuration devices have a four-pin interface: serial clock input (DCLK), serial data output (DATA), AS data input (ASDI), and an activelow chip select (nCS). This four-pin interface connects to Cyclone FPGA pins, as shown in Figure 13-5. Altera Corporation May 2003 13-7 Preliminary Cyclone Device Handbook, Volume 1 Figure 13-5. AS Configuration of a Single Cyclone FPGA VCC (1) VCC (1) VCC (1) 10 k Serial Configuration Device 10 k 10 k Cyclone FPGA nSTATUS CONF_DONE nCONFIG nCE GND nCEO N.C. (2) DATA DCLK nCS ASDI (3) DATA0 DCLK nCSO ASDO MSEL1 MSEL0 GND Notes to Figure 13-5: (1) (2) (3) Power up the ByteBlaster II Vcc with a 3.3-V supply. The nCEO pin is left unconnected. Cyclone FPGAs use the ASDO to ASDI path to control the configuration device. Connecting the MSEL[1..0] pins to 00 selects the AS configuration scheme. The Cyclone chip enable signal, nCE, must also be connected to ground for successful configuration. During system power up, both the Cyclone FPGA and serial configuration device enter a power-on reset (POR) period. As soon as the Cyclone FPGA enters POR, it drives nSTATUS low to indicate it is busy and drives CONF_DONE low to indicate that it has not been configured. After POR, which typically lasts 100 ms, the Cyclone FPGA releases nSTATUS and enters configuration mode when this signal is pulled high by the external 10-k resistor. The serial clock (DCLK) generated by the Cyclone FPGA controls the entire configuration cycle (see Figure 13-1 on page 13-2) and this clock line provides the timing for the serial interface. Cyclone FPGAs use an internal oscillator to generate DCLK. Typical DCLK frequency during AS configuration is 15 MHz. The serial configuration device latches input/control signals on the rising edge of DCLK and drives out configuration data on the falling edge. Cyclone FPGAs drive out control signals on the falling edge of DCLK and latch configuration data on the rising edge of DCLK. 13-8 Preliminary Altera Corporation May 2003 Configuration Schemes In configuration mode, the Cyclone FPGA enables the serial configuration device by driving the nCSO output pin low that is connected to the chip select (nCS) pin of the configuration device. The Cyclone FPGA's serial clock (DCLK) and serial data output (ASDO) pins are used to read configuration data. The configuration device provides data on its serial data output (DATA) pin that is connected to the DATA0 input on Cyclone FPGAs. After all configuration bits are received by the Cyclone FPGA, it releases the open-drain CONF_DONE pin allowing the external 10-k resistor to pull this signal to a high level. Initialization begins only after the CONF_DONE line reaches a high level. Initialization completes within 136 clock cycles and the device enters user mode. You can select the clock used for initialization by using the User Supplied Start-Up Clock option in the Quartus II software. The Quartus II software uses the 10-MHz internal oscillator by default to initialize the Cyclone FPGA. When you enable the User Supplied Start-Up Clock option, the software uses the CLKUSR pin as the initialization clock. If an error occurs during configuration, the Cyclone FPGA asserts the nSTATUS signal low indicating a data frame error, and the CONF_DONE signal will stay low. With the Auto-Restart Configuration on Frame Error option enabled in the Quartus II software, the Cyclone FPGA resets the configuration device by pulsing nCSO, releases nSTATUS after a reset time-out period (about 30 micro-seconds), and retries configuration. After successful configuration, the CONF_DONE signal is tri-stated by the target device and then pulled high by the pull-up resistor. All AS configuration pins, DATA0, DCLK, nCSO, and ASDO, have weak internal pull-up resistors. These pull-up resistors are always active. Configuring Multiple Devices (Cascading) You can configure multiple Cyclone FPGAs using a single serial configuration device. You can cascade multiple Cyclone FPGAs using the chip-enable (nCE) and chip-enable-out (nCEO) pins. The first device in the chain must have its nCE pin connected to ground. You must connect its nCEO chip-enable-out pin to the chip-enable (nCE) pin of the next device in the chain. When the first device captures all of its configuration data from the bit stream, it drives the nCEO pin low enabling the next device in the chain. You must leave the nCEO pin of the last device unconnected. This first Cyclone FPGA in the chain is the configuration master and controls configuration of the entire chain. You must connect its MSEL pins to select the AS configuration scheme. The remaining Cyclone FPGAs are Altera Corporation May 2003 13-9 Preliminary Cyclone Device Handbook, Volume 1 configuration slaves and you must connect their MSEL pins to select the PS configuration scheme. Figure 13-6 shows the pin connections for this setup. Figure 13-6. Configuring Multiple Devices Using a Serial Configuration Device (AS) VCC (1) VCC (1) VCC (1) 10 k 10 k 10 k Serial Configuration Device Cyclone FPGA nSTATUS CONF_DONE nCONFIG nCE nCEO GND Cyclone FPGA nSTATUS CONF_DONE nCONFIG nCE nCEO N.C. (2) VCC (3) DATA0 DCLK nCSO ASDO Master GND MSEL1 MSEL0 DATA0 DCLK MSEL1 MSEL0 Slave GND DATA DCLK nCS ASDI Notes to Figure 13-6: (1) (2) (3) Power up the ByteBlaster II Vcc with a 3.3-V supply. The nCEO pin is left unconnected. Connect MSEL0 to the Vcc supply voltage of the I/O Bank it resides in. As shown in Figure 13-6, the nSTATUS and CONF_DONE pins on all target FPGAs are connected together with external pull-up resistors. These pins are open-drain bidirectional pins on the FPGAs. When the first device asserts nCEO (after receiving all of its configuration data), it releases its CONF_DONE pin. But the subsequent devices in the chain keep this shared CONF_DONE line low until they have received their configuration data. When all target FPGAs in the chain have received their configuration data and have released CONF_DONE, the pull-up resistor drives a high level on this line and all devices simultaneously enter initialization mode. If an error occurs at any point during configuration, the nSTATUS line is driven by the failing FPGA. If you enable the Auto Restart Configuration on Frame Error option, reconfiguration of the entire chain begins. 13-10 Preliminary Altera Corporation May 2003 Configuration Schemes Furthermore, while you can cascade Cyclone FPGAs, serial configuration devices cannot be cascaded or chained together. If the configuration bit stream size exceeds the capacity of a serial configuration device, you must select a larger configuration device and/or enable the compression feature. While configuring multiple devices, the size of the bit stream is the sum of the individual devices' configuration bit streams. Programming Serial Configuration Devices Serial configuration devices are non-volatile, flash-memory-based devices. You can program these devices in-system using the ByteBlasterTM II download cable. Alternatively, you can program them using the Altera Programming Unit (APU) or supported third-party programmers. You can perform in-system programming of serial configuration devices via the AS programming interface. During in-system programming, the download cable disables FPGA access to the AS interface by driving the chip-enable nCE pin high. Cyclone FPGAs are also held in reset by a low level on nCONFIG. After programming is complete, the download cable releases nCE and nCONFIG, allowing the pull-down and pull-up resistor to drive GND and VCC, respectively. Figure 13-7 shows the download cable connections to the serial configuration device. f For more information on the ByteBlaster II cable, see the ByteBlaster II Download Cable Data Sheet. Altera Corporation May 2003 13-11 Preliminary Cyclone Device Handbook, Volume 1 Figure 13-7. In-System Programming of Serial Configuration Devices VCC (1) 10 k VCC (1) VCC (1) 10 k Cyclone FPGA CONF_DONE nSTATUS Serial Configuration Device 10 k DATA DCLK nCS ASDI DATA0 DCLK nCSO ASDO MSEL1 MSEL0 nCONFIG nCEO N.C. (2) 10 k nCE GND VCC (3) Pin 1 ByteBlaser II 10-Pin Male Header Notes to Figure 13-7: (1) (2) (3) Connect these pull-up resistors to 3.3-V supply. The nCEO pin is left unconnected. Power up the ByteBlaster II Vcc with a 3.3-V supply. You can program serial configuration devices by using the Quartus II software with the APU and the appropriate configuration device programming adapter. All serial configuration devices are offered in an eight-pin small outline integrated circuit (SOIC) package and can be programmed using the PLMSEPC-8 adapter. In production environments, Serial Configuration devices can be programmed using multiple methods. Altera programming hardware (APU) or other third-party programming hardware can be used to program blank Serial Configuration devices before they are mounted onto PCBs. Alternatively, you can use an on-board microprocessor to program the Serial Configuration device in-system using C-based software drivers provided by Altera. For more information on these and other new methods, please refer to the Cyclone Literature web page. 13-12 Preliminary Altera Corporation May 2003 Configuration Schemes Passive Serial Configuration Cyclone FPGAs also feature the PS configuration scheme supported by all Altera FPGAs. In the PS scheme, an external host (configuration device, embedded processor, or host PC) controls configuration. Configuration data is clocked into the target Cyclone FPGAs via the DATA0 pin at each rising edge of DCLK. The configuration waveforms for this scheme are shown in Figure 13-8. Figure 13-8. PS Configuration Cycle Waveform D(N - 1) nCONFIG nSTATUS CONF_DONE (1) DCLK DATA High-Z User I/O Pins (2) INIT_DONE (3) MODE Configuration Configuration Initialization User D0 High-Z D1 D2 D3 DN High-Z (4) (5) User I/O Notes to Figure 13-8: (1) (2) (3) (4) (5) During initial power up and configuration, CONF_DONE is low. After configuration, CONF_DONE goes high to indicate successful configuration. If the device is reconfigured, CONF_DONE goes low after nCONFIG is driven low. User I/O pins are tri-stated during configuration. Cyclone FPGAs also have a weak pull-up resistor on I/O pins during configuration. After initialization, the user I/O pins perform the function assigned in the user's design. When used, the optional INIT_DONE signal is high when nCONFIG is low before configuration and during the first 136 clock cycles of configuration. In user mode, DCLK should be driven high or low when using the PS configuration scheme. When using the AS configuration scheme, DCLK is a Cyclone output pin and should not be driven externally. In user mode, DATA0 should be driven high or low. PS Configuration using Configuration Device In the PS configuration device scheme, nCONFIG is usually tied to VCC (when using EPC16, EPC8, EPC4, or EPC2 devices, you can connect nCONFIG to nINIT_CONF). Upon device power-up, the target Cyclone FPGA senses the low-to-high transition on nCONFIG and initiates configuration. The target device then drives the open-drain CONF_DONE pin low, which in-turn drives the configuration device's nCS pin low. When exiting POR, both the target and configuration device release the open-drain nSTATUS pin (typically Cyclone POR lasts 100 ms). Before configuration begins, the configuration device goes through a POR delay of up to 100 ms (maximum) to allow the power supply to stabilize. You must power the Cyclone FPGA before or during the POR Altera Corporation May 2003 13-13 Preliminary Cyclone Device Handbook, Volume 1 time of the enhanced configuration device. During POR, the configuration device drives its OE pin low. This low signal delays configuration because the OE pin is connected to the target device's nSTATUS pin. When the target and configuration devices complete POR, they both release the nSTATUS to OE line, which is then pulled high by a pull-up resistor. When configuring multiple devices, configuration does not begin until all devices release their OE or nSTATUS pins. When all devices are ready, the configuration device clocks out DATA and DCLK to the target devices using an internal oscillator. After successful configuration, the Cyclone FPGA starts initialization using the 10-MHz internal oscillator as the reference clock. The CONF_DONE pin is released by the target device and then pulled high by a pull-up resistor. When initialization is complete, the target Cyclone FPGA enters user mode. If an error occurs during configuration, the target device drives its nSTATUS pin low, resetting itself internally and resetting the configuration device. If you turn on the Auto-Restart Configuration on Frame Error option, the device reconfigures automatically if an error occurs. To set this option, select Compiler Settings (Processing menu), and click on the Chips & Devices tab. Select Device & Pin Options, and click on the Configuration tab. If the Auto-Restart Configuration on Frame Error option is turned off, the external system (configuration device or microprocessor) must monitor nSTATUS for errors and then pulse nCONFIG low to restart configuration. The external system can pulse nCONFIG if it is under system control rather than tied to VCC. When configuration is complete, the target device releases CONF_DONE, which disables the configuration device by driving nCS high. The configuration device drives DCLK low before and after configuration. In addition, if the configuration device sends all of its data and then detects that CONF_DONE has not gone high, it recognizes that the target device has not configured successfully. (For CONF_DONE to reach a high state, enhanced configuration devices wait for 64 DCLK cycles after the last configuration bit. EPC2 devices wait for 16 DCLK cycles.) In this case, the configuration device pulses its OE pin low for a few microseconds, driving the target device's nSTATUS pin low. If the Auto-Restart Configuration on Frame Error option is set in the Quartus II software, the target device resets and then releases its nSTATUS pin after a reset timeout period. When nSTATUS returns high, the configuration device reconfigures the target device. 13-14 Preliminary Altera Corporation May 2003 Configuration Schemes You should not pull CONF_DONE low to delay initialization. Instead, use the Quartus II software's User-Supplied Start-Up Clock option to synchronize the initialization of multiple devices that are not in the same configuration chain. Devices in the same configuration chain initialize together since their CONF_DONE pins are tied together. For more information on this option, see "Device Options" on page 13-41. CONF_DONE goes high during the first few clock cycles of initialization. Hence when using the CLKUSR feature you would not see the CONF_DONE signal high until you start clocking CLKUSR. However, the device does retain configuration data and waits for these initialization clocks to release CONF_DONE and go into user mode. 1 When using internal pull-up resistors on configuration devices, power the supply voltage on the Cyclone FPGA I/O pins (VCCIO) to 3.3-V. EPC2, EPC4, EPC8, and EPC16 devices support 3.3-V operation but not 2.5-V operation. Therefore, you must set the VCCIO voltages for the banks where programming pins reside to 3.3 V. Figure 13-9 shows how to configure one Cyclone FPGA with one configuration device. Figure 13-9. Single Device Configuration Circuit VCC (1) VCC (1) VCC (1) Cyclone FPGA DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1 GND nCEO nCE N.C. (3) 10 k 10 k 10 k Configuration Device DCLK DATA OE nCS nINIT_CONF (2) VCC (4) GND Notes to Figure 13-9: (1) The pull-up resistor should be connected to the same supply voltage as the configuration device. This pull-up resistor is 10 k. The EPC16, EPC8, EPC4, and EPC2 devices' OE and nCS pins have internal, user-configurable pull-up resistors. If you use internal pull-up resistors, do not use external pull-up resistors on these pins. The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices and has an internal pull-up resistor that is always active. If nINIT_CONF is not used, nCONFIG must be pulled to VCC through a resistor. The nCEO pin is left unconnected for the last device in the chain. Connect MSEL0 to the Vcc supply voltageof I/O Bank it resides in. (2) (3) (4) Altera Corporation May 2003 13-15 Preliminary Cyclone Device Handbook, Volume 1 Configuring Multiple Cyclone FPGAs You can use a single configuration device to configure multiple Cyclone FPGAs. In this setup, the nCEO pin of the first device is connected to the nCE pin of the second device in the chain. If there are additional devices, connect the nCE pin of the next device to the nCEO pin of the previous device. You should leave the nCEO pin on the last device in the chain unconnected. To configure properly, all of the target device CONF_DONE and nSTATUS pins must be tied together. Figure 13-10 shows an example of configuring multiple Cyclone FPGAs using a single configuration device. Figure 13-10. Configuring Multiple Cyclone FPGAs with a Single Configuration Device VCC (1) VCC (1) VCC (1) 10 k 10 k 10 k VCC (6) Cyclone FPGA 2 DCLK DATA0 nSTATUS CONF_DONE nCONFIG VCC (6) Cyclone FPGA 1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG Configuration Device (2) DCLK DATA OE nCS nCASC nINIT_CONF (4), (5) MSEL0 MSEL1 GND N.C. nCEO (3) MSEL0 MSEL1 GND nCE nCEO nCE GND Notes to Figure 13-10: (1) The pull-up resistor should be connected to the same supply voltage as the configuration device. The EPC16, EPC8, EPC4, and EPC2 devices' OE and nCS pins have internal, user-configurable pull-up resistors. If you use internal pull-up resistors, do not use external pull-up resistors on these pins. EPC16, EPC8, and EPC4 configuration devices cannot be cascaded. The nCEO pin is left unconnected for the last device in the chain. The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices. If nINIT_CONF is not used, nCONFIG must be pulled to VCC through a resistor. The nINIT_CONF pin has an internal pull-up resistor that is always active in EPC16, EPC8, EPC4, and EPC2 devices. These devices do not need an external pull-up resistor on the nINIT_CONF pin. Connect MSEL0 to the Vcc supply voltageof I/O Bank it resides in. (2) (3) (4) (5) (6) When performing multi-device PS configuration, you must generate the configuration device programming file (.sof) from each project. Then you must combine multiple .sof files using the Quartus II software through the Convert Programming Files dialog box. 13-16 Preliminary Altera Corporation May 2003 Configuration Schemes f For more information on how to create Programmer Object Files (.pof) for enhanced configuration devices, see Application Note 218: Using Enhanced Configuration Devices. For a description of the various configuration and programming files, see "Device Configuration Files" on page 13-47. After the first Cyclone FPGA completes configuration during multidevice configuration, its nCEO pin activates the second device's nCE pin, prompting the second device to begin configuration. Because all device CONF_DONE pins are tied together, all devices initialize and enter user mode at the same time. In addition, all nSTATUS pins are tied together; therefore, if any device (including the configuration device) detects an error, configuration stops for the entire chain. Also, if the configuration device does not detect CONF_DONE going high at the end of configuration, it resets the chain by pulsing its OE pin low for a few microseconds. For CONF_DONE to reach a high state, enhanced configuration devices wait for 64 DCLK cycles after the last configuration bit. EPC2 devices wait for 16 DCLK cycles. If the Auto-Restart Configuration on Frame Error option is turned on in the Quartus II software, the Cyclone FPGA releases its nSTATUS pins after a reset time-out period (about 30 micro-seconds). When the nSTATUS pins are released and pulled high, the configuration device reconfigures the chain. If the Auto-Restart Configuration on Frame Error option is not turned on, the devices drive nSTATUS low until they are reset with a low pulse on nCONFIG. You can also cascade several EPC2 configuration devices to configure multiple Cyclone FPGAs. When all data from the first configuration device is sent, it drives nCASC low, which in turn drives nCS on the subsequent EPC2 device. Because a configuration device requires less than one clock cycle to activate a subsequent configuration device, the data stream is uninterrupted. You cannot cascade EPC16, EPC8, and EPC4 configuration devices. Programming Configuration Devices Enhanced configuration devices (EPC4, EPC8, and EPC16 devices) and EPC2 devices support in-system programming via JTAG. You can program these configuration devices using the Quartus II software and a download cable (e.g., ByteBlaster II, MasterBlasterTM, or ByteBlasterMVTM cables). Altera Corporation May 2003 13-17 Preliminary Cyclone Device Handbook, Volume 1 You can also program configuration devices using the Quartus II software, the APU, and the appropriate configuration device programming adapter. Table 13-4 shows which programming adapter to use with each configuration device. Table 13-4. Programming Adapters Device EPC16 EPC8 EPC4 EPC2 EPC1 Package 88-pin Ultra FineLine BGA 100-pin PQFP 100-pin PQFP 100-pin PQFP 20-pin J-Lead 32-pin TQFP 8-pin DIP 20-pin J-Lead (R) Adapter PLMUEPC-88 PLMQEPC-100 PLMQEPC-100 PLMQEPC-100 PLMJ1213 PLMT1213 PLMJ1213 PLMJ1213 PS Configuration Using a Download Cable Using a download cable in PS configuration, an intelligent host (e.g., your PC) transfers data from a storage device (e.g., your hard drive) to the Cyclone FPGA through a ByteBlaster II, MasterBlaster, or ByteBlasterMV cable. To initiate configuration in this scheme, the download cable generates a low-to-high transition on the nCONFIG pin. The programming hardware then sends the configuration data one bit at a time on the device's DATA0 pin. The data is clocked into the target device using DCLK until the CONF_DONE goes high. When using programming hardware for the Cyclone FPGA, turning on the Auto-Restart Configuration on Frame Error option does not affect the configuration cycle because the Quartus II software must restart configuration when an error occurs. Figure 13-11 shows the PS configuration setup for the Cyclone FPGA using a ByteBlaster II, MasterBlaster, or ByteBlasterMV cable. 13-18 Preliminary Altera Corporation May 2003 Configuration Schemes Figure 13-11. PS Configuration Circuit with ByteBlaster II, MasterBlaster, or ByteBlasterMV Cable VCC (1) VCC (1) 10 k (4) (4) 10 k VCC (1) 10 k VCC (5) MSEL0 MSEL1 nCE GND VCC (1) VCC (1) 10 k Cyclone Device CONF_DONE nSTATUS 10 k ByteBlaster II, MasterBlaster, or ByteBlasterMV 10-Pin Male Header Pin 1 VCC (2) DCLK DATA0 nCONFIG GND VIO (3) Shield GND Notes to Figure 13-11: (1) (2) (3) (4) You should connect the pull-up resistor to the same supply voltage as the MasterBlaster (VIO pin) or ByteBlasterMV cable. Power supply voltage: VCC = 3.3-V for the ByteBlaster II, MasterBlaster, and ByteBlasterMV cable. Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device's VCCIO. This pin is a no-connect pin for the ByteBlasterMV header. The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration scheme used on your board. This is to ensure that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed. Connect MSEL0 to the Vcc supply voltageof I/O Bank it resides in. (5) You can use the download cable to configure multiple Cyclone FPGAs by connecting each device's nCEO pin to the subsequent device's nCE pin. All other configuration pins are connected to each device in the chain. Because all CONF_DONE pins are tied together, all devices in the chain initialize and enter user mode at the same time. In addition, because the nSTATUS pins are tied together, the entire chain halts configuration if any device detects an error. In this situation, the Quartus II software must restart configuration; the Auto-Restart Configuration on Frame Error option does not affect the configuration cycle. Figure 13-12 shows how to configure multiple Cyclone FPGAs with a ByteBlaster II, MasterBlaster, or ByteBlasterMV cable. Altera Corporation May 2003 13-19 Preliminary Cyclone Device Handbook, Volume 1 Figure 13-12. Multi-Device PS Configuration with a ByteBlaster II, MasterBlaster, or ByteBlasterMV Cable VCC (1) 10 k (5) VCC (1) VCC (1) 10 k (5) VCC (6) 10 k VCC (1) 10 k ByteBlaster II, MasterBlaster, or ByteBlasterMV 10-Pin Male Header (Passive Serial Mode) Pin 1 Cyclone FPGA 1 MSEL0 MSEL1 CONF_DONE nSTATUS DCLK VCC (2) VCC (1) 10 k GND GND nCE VIO (3) DATA0 nCONFIG VCC nCEO GND Cyclone FPGA 2 MSEL0 MSEL1 CONF_DONE nSTATUS DCLK GND nCE DATA0 nCONFIG nCEO N.C. (4) Notes to Figure 13-12: (1) (2) (3) (4) (5) You should connect the pull-up resistor to the same supply voltage as the MasterBlaster (VIO pin) or ByteBlasterMV cable. Power supply voltage: VCC = 3.3-V for the ByteBlaster II, MasterBlaster, and ByteBlasterMV cable. VIO is a reference voltage for the MasterBlaster output driver. VIO should match the device's VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. The nCEO pin is left unconnected for the last device in the chain. The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration scheme used on your board. This is to ensure that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed. Connect MSEL0 to the Vcc supply voltageof I/O Bank it resides in. (6) If you are using a ByteBlaster II, MasterBlaster, or ByteBlasterMV cable to configure device(s) on a board that also is populated with configuration devices, you should electrically isolate the configuration devices from the target device(s) and cable. One way to isolate the configuration devices is to add logic, such as a multiplexer, that can select between the configuration devices and the cable. The multiplexer allows bidirectional transfers on the nSTATUS and CONF_DONE signals. Another option is to 13-20 Preliminary Altera Corporation May 2003 Configuration Schemes add switches to the five common signals (CONF_DONE, nSTATUS, DCLK, nCONFIG, and DATA0) between the cable and the configuration devices. The last option is to remove the configuration devices from the board when configuring with the cable. Figure 13-13 shows a combination of a configuration device and a ByteBlaster II, MasterBlaster, or ByteBlasterMV cable to configure a Cyclone FPGA. Figure 13-13. Configuring with a Combined PS & Configuration Device Scheme VCC (1) 10 k (7) VCC (8) VCC (1) 10 k Cyclone FPGA MSEL0 MSEL1 CONF_DONE nSTATUS DCLK VCC (1) 10 k VCC (1) ByteBlaster II, MasterBlaster, or ByteBlasterMV 10-Pin Male Header (Passive Serial Mode) VCC (1) Pin 1 VCC (2) 10 k 10 k (7) GND VIO (3) nCE GND nCEO N.C. (4) DATA0 nCONFIG (5) (5) (5) GND Configuration Device (5) (5) DCLK DATA OE nCS nINIT_CONF (6) Notes to Figure 13-13: (1) (2) (3) (4) (5) You should connect the pull-up resistor to the same supply voltage as the configuration device. Power supply voltage: VCC = 3.3-V for the ByteBlaster II, MasterBlaster, and ByteBlasterMV cable. Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the target device's VCCIO. This is a no-connect pin for the ByteBlasterMV header. The nCEO pin is left unconnected. You should not attempt configuration with a ByteBlaster II, MasterBlaster, or ByteBlasterMV cable while a configuration device is connected to a Cyclone FPGA. Instead, you should either remove the configuration device from its socket when using the download cable or place a switch on the five common signals between the download cable and the configuration device. Remove the ByteBlaster II, MasterBlaster, or ByteBlasterMV cable when configuring with a configuration device. If nINIT_CONF is not used, nCONFIG must be pulled to VCC either directly or through a resistor. The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration scheme used on your board. This is to ensure that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed. Connect MSEL0 to the Vcc supply voltageof I/O Bank it resides in. (6) (7) (8) Altera Corporation May 2003 13-21 Preliminary Cyclone Device Handbook, Volume 1 f For more information on how to use the ByteBlaster II, MasterBlaster, or ByteBlasterMV cables, see the following documents: ByteBlaster II Parallel Port Download Cable Data Sheet MasterBlaster Serial/USB Communications Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet PS Configuration from a Microprocessor In PS configuration with a microprocessor, a microprocessor transfers data from a storage device to the target Cyclone FPGA. To initiate configuration in this scheme, the microprocessor must generate a low-tohigh transition on the nCONFIG pin and the target device must release nSTATUS. The microprocessor then places the configuration data one bit at a time on the DATA0 pin of the Cyclone FPGA. The least significant bit (LSB) of each data byte must be presented first. Data is clocked continuously into the target device using DCLK until the CONF_DONE signal goes high. The Cyclone FPGA starts initialization using the internal oscillator after all configuration data is transferred. The device's CONF_DONE pin goes high to show successful configuration and the start of initialization. Driving DCLK to the device after configuration does not affect device operation. Since the PS configuration scheme is a synchronous scheme, the configuration clock speed must be below the specified maximum frequency to ensure successful configuration. Maximum DCLK frequency supported by Cyclone FPGAs is 100 MHz (See Table 13-5 on page 13-24). No maximum DCLK period (i.e., minimum DCLK frequency) exists. You can pause configuration by halting DCLK for an indefinite amount of time. If the target device detects an error during configuration, it drives its nSTATUS pin low to alert the microprocessor. The microprocessor can then pulse nCONFIG low to restart the configuration process. Alternatively, if the Auto-Restart Configuration on Frame Error option is turned on in the Quartus II software, the target device releases nSTATUS after a reset time-out period. After nSTATUS is released, the microprocessor can reconfigure the target device without needing to pulse nCONFIG low. The microprocessor can also monitor the CONF_DONE and INIT_DONE pins to ensure successful configuration and initialization. If the microprocessor sends all data but CONF_DONE and INIT_DONE has not gone high, it must reconfigure the target device. CONF_DONE should go 13-22 Preliminary Altera Corporation May 2003 Configuration Schemes high within 1 ms, and INIT_DONE should go high within 15 ms. Figure 13-14 shows the circuit for PS configuration with a microprocessor. Figure 13-14. PS Configuration Circuit with a Microprocessor Memory ADDR DATA0 VCC 10 k VCC VCC (2) 10 k Cyclone Device MSEL0 MSEL1 GND nCEO DATA0 nCONFIG DCLK N.C. (1) CONF_DONE nSTATUS nCE Microprocessor GND Note to Figure 13-14: (1) (2) The nCEO pin is left unconnected. Connect MSEL0 to the Vcc supply voltageof I/O Bank it resides in. Configuring Cyclone FPGAs with the MicroBlaster Software The MicroBlasterTM software driver allows you to configure Altera FPGAs, including Cyclone FPGAs, through the ByteBlaster II or ByteBlasterMV cable in PS mode. The MicroBlaster software driver supports a Raw Binary File (.rbf) programming input file and is targeted for embedded PS configuration. The source code is developed for the Windows NT operating system, although you can customize it to run on other operating systems. For more information on the MicroBlaster software driver, see the Configuring the MicroBlaster Passive Serial Software Driver White Paper and source files on the Altera web site at www.altera.com. Passive Serial Timing For successful configuration using the PS scheme, several timing parameters such as setup, hold, and maximum clock frequency must be satisfied. The enhanced configuration and EPC2 devices are designed to meet these interface timing specifications. If you use a microprocessor or another intelligent host to control the PS interface, ensure that you meet these timing requirements. Altera Corporation May 2003 13-23 Preliminary Cyclone Device Handbook, Volume 1 Figure 13-15 shows the PS timing waveform for Cyclone FPGAs. Figure 13-15. PS Timing Waveform for Cyclone FPGAs tCF2ST1 tCFG nCONFIG tCF2CK nSTATUS (1) tSTATUS tCF2ST0 t tCF2CD tST2CK CLK CONF_DONE (2) tCH tCL DCLK (3) tDH DATA Bit 0 Bit 1 Bit 2 Bit 3 tDSU User I/O INIT_DONE High-Z User Mode Bit n (4) tCD2UM Notes to Figure 13-15: (1) (2) (3) (4) Upon power-up, the Cyclone FPGA holds nSTATUS low for about 100 ms. Upon power-up and before configuration, CONF_DONE is low. In user mode, DCLK should be driven high or low when using the PS configuration scheme. When using the AS configuration scheme, DCLK is a Cyclone output pin and should not be driven externally. DATA should not be left floating after configuration. It should be driven high or low, whichever is more convenient. Table 13-5 contains the PS timing information for Cyclone FPGAs. Table 13-5. PS Timing Parameters for Cyclone Devices Symbol tCF2CD tCF2ST0 tCF2ST1 tCFG tSTATUS tCF2CK tST2CK tDSU tDH Note (1) (Part 1 of 2) Min Max 800 800 40 (4) 40 10 40 1 7 0 40 (4) Parameter nCONFIG low to CONF_DONE low nCONFIG low to nSTATUS low nCONFIG high to nSTATUS high nCONFIG low pulse width (2) nSTATUS low pulse width nCONFIG high to first rising edge on DCLK nSTATUS high to first rising edge on DCLK Data setup time before rising edge on DCLK Data hold time after rising edge on DCLK Units ns ns s s s s s ns ns 13-24 Preliminary Altera Corporation May 2003 Configuration Schemes Table 13-5. PS Timing Parameters for Cyclone Devices Symbol tCH tCL tCLK fMAX tCD2UM (1) (2) Note (1) (Part 2 of 2) Min 4 4 10 100 6 20 Parameter DCLK high time DCLK low time DCLK period DCLK maximum frequency CONF_DONE high to user mode (3) Max Units ns ns ns MHz s Notes to Table 13-5: This information is preliminary. This value applies only if the internal oscillator is selected as the clock source for device initialization. If the clock source is CLKUSR, multiply the clock period by 270 to obtain this value. CLKUSR must be running during this period to reset the device. The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for device initialization. If the clock source is CLKUSR, multiply the clock period by 140 to obtain this value. You can obtain this value if you do not delay configuration by extending the nSTATUS low-pulse width. (3) (4) JTAG-Based Configuration JTAG has developed a specification for boundary-scan testing. This boundary-scan test (BST) architecture offers the capability to efficiently test components on printed circuit boards (PCBs) with tight lead spacing. The BST architecture can test pin connections without using physical test probes and capture functional data while a device is operating normally. You can also use the JTAG circuitry to shift configuration data into Cyclone FPGAs. The Quartus II software automatically generates .sof files that can be used for JTAG configuration. f For more information on JTAG boundary-scan testing, see Application Note 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices. A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK. Cyclone FPGAs do not support the optional TRST pin. The three JTAG input pins, TCK, TDI, and TMS, have weak internal pull-up resistors. All user I/O pins are tri-stated during JTAG configuration. Cyclone is designed such that JTAG instructions have precedence over any device operating modes. So JTAG configuration can take place without waiting for other configuration to complete (e.g., configuration with serial or enhanced configuration devices). If you attempt JTAG configuration in Cyclone FPGAs during non-JTAG configuration, nonJTAG configuration will be terminated and JTAG configuration will be initiated. Altera Corporation May 2003 13-25 Preliminary Cyclone Device Handbook, Volume 1 Table 13-6 shows each JTAG pin's function. Table 13-6. JTAG Pin Descriptions Pin TDI TDO Description Test data input Test data output Function Serial input pin for instructions as well as test and programming data. Data is shifted in on the rising edge of TCK. Serial data output pin for instructions as well as test and programming data. Data is shifted out on the falling edge of TCK. The pin is tri-stated if data is not being shifted out of the device. Input pin that provides the control signal to determine the transitions of the Test Access Port (TAP) controller state machine. Transitions within the state machine occur on the rising edge of TCK. Therefore, TMS must be set up before the rising edge of TCK. TMS is evaluated on the rising edge of TCK. The clock input to the BST circuitry. Some operations occur at the rising edge, while others occur at the falling edge. TMS Test mode select TCK Test clock input JTAG Configuration Using a Download Cable During JTAG configuration, data is downloaded to the device on the board through a ByteBlaster II, ByteBlasterMV, or MasterBlaster download cable. Configuring devices through a cable is similar to programming devices in-system. See Figure 13-16 for pin connection information. 13-26 Preliminary Altera Corporation May 2003 Configuration Schemes Figure 13-16. JTAG Configuration of Single Cyclone FPGA VCC VCC 10 k GND 10 k VCC VCC 10 k Cyclone Device 10 k nCE TCK TDO (2) (2) (2) (2) (2) nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1 DATA0 DCLK TMS TDI ByteBlaster II, MasterBlaster, or ByteBlasterMV 10-Pin Male Header (Top View) Pin 1 VCC (1) GND VIO (3) 10 k GND GND Notes to Figure 13-16: (1) (2) You should connect the pull-up resistor to the same supply voltage as the download cable. You should connect the nCONFIG, MSEL0, and MSEL1 pins to support a non-JTAG configuration scheme. If you only use JTAG configuration, connect nCONFIG to VCC, and MSEL0 and MSEL1 to ground. Pull DATA0 and DCLK to high or low. VIO is a reference voltage for the MasterBlaster output driver. VIO should match the device's VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. (3) To configure a single device in a JTAG chain, the programming software places all other devices in bypass mode. In bypass mode, devices pass programming data from the TDI pin to the TDO pin through a single bypass register without being affected internally. This scheme enables the programming software to program or verify the target device. Configuration data driven into the device appears on the TDO pin one clock cycle later. Cyclone FPGAs have dedicated JTAG pins. Not only can you perform JTAG testing on Cyclone FPGAs before and after, but also during configuration. While other device families do not support JTAG testing during configuration, Cyclone FPGAs support the BYPASS, IDCODE, and SAMPLE instructions during configuration without interrupting configuration. All other JTAG instructions may only be issued by first interrupting configuration and reprogramming I/O pins using the CONFIG_IO instruction. Altera Corporation May 2003 13-27 Preliminary Cyclone Device Handbook, Volume 1 The CONFIG_IO instruction allows I/O buffers to be configured via the JTAG port, and when issued, interrupts configuration. This instruction allows you to perform board-level testing prior to configuring the Cyclone FPGA or waiting for a configuration device to complete configuration. Once configuration has been interrupted and JTAG testing is complete, the part must be reconfigured via JTAG (PULSE_CONFIG instruction) or by pulsing nCONFIG low. The chip-wide reset and output enable pins on Cyclone FPGAs do not affect JTAG boundary-scan or programming operations. Toggling these pins does not affect JTAG operations (other than the usual boundary-scan operation). When designing a board for JTAG configuration of Cyclone FPGAs, you should consider the regular configuration pins. Table 13-7 shows how you should connect these pins during JTAG configuration. Table 13-7. JTAG Termination of Unused Pins Signal nCE nSTATUS CONF_DONE nCONFIG MSEL0, MSEL1 DCLK DATA0 (1) Description Drive all Cyclone devices in the chain low by connecting nCE to ground, pulling it down via a resistor, or driving it low by some control circuitry. Pulled to VCC through a 10-k resistor. When configuring multiple devices in the same JTAG chain, pull up each nSTATUS pin to VCC individually. (1) Pulled to VCC through a 10-k resistor. When configuring multiple devices in the same JTAG chain, pull up each CONF_DONE pin to VCC individually. (1) Driven high by connecting to VCC, pulling up through a resistor, or driving it high by some control circuitry. Do not leave these pins floating. These pins support whichever non-JTAG configuration is used in production. If only JTAG configuration is used, you should tie these pins to ground. Do not leave these pins floating. Drive low or high, whichever is more convenient. Do not leave these pins floating. Drive low or high, whichever is more convenient. Note to Table 13-7: nSTATUS going low in the middle of JTAG configuration indicates that an error has occurred; CONF_DONE going high at the end of JTAG configuration indicates successful configuration. JTAG Configuration of Multiple Devices When programming a JTAG device chain, one JTAG-compatible header, such as the ByteBlaster II header, is connected to several devices. The number of devices in the JTAG chain is limited only by the drive capacity of the download cable. However, when four or more devices are connected in a JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an on-board buffer. 13-28 Preliminary Altera Corporation May 2003 Configuration Schemes JTAG-chain device configuration is ideal when the system contains multiple devices, or when testing your system using JTAG BST circuitry. Figure 13-17 shows multi-device JTAG configuration. Figure 13-17. Multi-Device JTAG Configuration VCC VCC VCC VCC VCC VCC ByteBlaser II, MasterBlaster, or ByteBlasterMV 10-Pin Male Header VCC 10 k 10 k 10 k 10 k 10 k Cyclone FPGA nSTATUS (4) (4) (4) (4) (4) DATA0 DCLK nCONFIG MSEL1 CONF_DONE MSEL0 nCE TDI TMS TDO TCK 10 k Cyclone FPGA nSTATUS DATA0 DCLK nCONFIG MSEL1 CONF_DONE MSEL0 nCE TDI TMS TDO Cyclone FPGA nSTATUS DATA0 DCLK nCONFIG MSEL1 CONF_DONE MSEL0 nCE TDI TMS TDO TCK Pin 1 (3) VCC VCC (3) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) VIO (5) TCK (3) Notes to Figure 13-17: (1) (2) (3) (4) Cyclone, APEXTM II, APEX 20K, MercuryTM, ACEX(R) 1K, and FLEX(R) 10K devices can be placed within the same JTAG chain for device programming and configuration. For more information on all configuration pins connected in this mode, refer to Table 13-6 on page 13-26. These pull-up/pull-down resistors are 10 k. Connect the nCONFIG, MSEL0, and MSEL1 pins to support a non-JTAG configuration scheme. If only JTAG configuration is used, connect nCONFIG to VCC, and MSEL0 and MSEL1 to ground. Pull DATA0 and DCLK to either high or low. VIO is a reference voltage for the MasterBlaster output driver. VIO should match the device's VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. (5) The Quartus II software verifies successful JTAG configuration upon completion. The software checks the state of CONF_DONE through the JTAG port. If CONF_DONE is not high, the Quartus II software indicates that configuration has failed. If CONF_DONE is high, the software indicates that configuration was successful. 1 If VCCIO is tied to 3.3-V, both the I/O pins and the JTAG TDO port drive at 3.3-V levels. Figure 13-18 shows the JTAG configuration of a Cyclone FPGA with a microprocessor. Altera Corporation May 2003 13-29 Preliminary Cyclone Device Handbook, Volume 1 Figure 13-18. JTAG Configuration of Cyclone FPGAs with a Microprocessor Memory ADDR DATA (1) (2) (2) MSEL1 nCONFIG MSEL0 DATA0 DCLK TDI TCK TDO TMS nSTATUS CONF_DONE (1) (1) VCC 10 k VCC 10 k Cyclone FPGA Microprocessor Notes to Figure 13-18: (1) Connect the nCONFIG, MSEL1, and MSEL0 pins to support a non-JTAG configuration scheme. If your design only uses JTAG configuration, connect the nCONFIG pin to VCC and the MSEL1 and MSEL0 pins to ground. Pull DATA0 and DCLK to either high or low. (2) Connecting the JTAG Chain to the Embedded Processor There are two ways to connect the JTAG chain to the embedded processor. The most straightforward method is to connect the embedded processor directly to the JTAG chain. In this method, four of the processor pins are dedicated to the JTAG interface, saving board space but reducing the number of available embedded processor pins. Figure 13-19 illustrates the second method, which is to connect the JTAG chain to an existing bus through an interface programmable logic device (PLD). In this method, the JTAG chain becomes an address on the existing bus. The processor then reads from or writes to the address representing the JTAG chain. 13-30 Preliminary Altera Corporation May 2003 Configuration Schemes Figure 13-19. Embedded System Block Diagram Embedded System VCC TDI TMS to/from ByteBlasterMV TCK TDO Interface Logic (Optional) VCC 10 k 10 k TDI Control 8 4 20 adr[19..0] Control TMS TDI TCK d[3..0] TDO TMS TCK TDO d[7..0] Any JTAG Device MAX 9000, MAX 9000A, MAX 7000S, MAX 7000A, MAX 7000AE, or MAX 3000 Device VCC VCC TDI TRST nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1 nCE TDO GND 10 k VCC 10 k Embedded Processor Control 8 20 20 TDI d[7..0] adr[19..0] EPROM or System Memory TMS TCK TDO adr[19..0] TMS TCK TDI TMS MSEL1 TCK MSEL0 (1) (1) Any Cyclone, FLEX 10K, FLEX 10KA, FLEX10KE, APEX 20K, or APEX 20KE Device (2) (2) (1) DATA0 DCLK nCONFIG TDO Cyclone FPGA 10 k GND Notes to Figure 13-19: (1) (2) Connect the nCONFIG, MSEL1, and MSEL0 pins to support a non-JTAG configuration scheme. If your design only uses JTAG configuration, connect the nCONFIG pin to VCC and the MSEL1 and MSEL0 pins to ground. Pull DATA0 and DCLK to either high or low. Configuring Cyclone FPGAs with JRunner JRunner is a software driver that allows you to configure Altera FPGAs, including Cyclone FPGAs, through the ByteBlaster II or ByteBlasterMV cables in JTAG mode. The programming input file supported is in .rbf format. JRunner also requires a Chain Description File (.cdf) generated by the Quartus II software. JRunner is targeted for embedded JTAG configuration. The source code has been developed for the Windows NT operating system (OS). You can customize the code to make it run on Altera Corporation May 2003 13-31 Preliminary Cyclone Device Handbook, Volume 1 other platforms. For more information on the JRunner software driver, see JRunner Software Driver: An Embedded Solution to the JTAG Configuration and the source files on the Altera web site. Jam STAPL Jam STAPL, JEDEC standard JESD-71, is a standard file format for insystem programmability (ISP) purposes. Jam STAPL supports programming or configuration of programmable devices and testing of electronic systems, using the IEEE 1149.1 JTAG interface. Jam STAPL is a freely licensed open standard. 1 Both JTAG connection methods should include space for the MasterBlaster or ByteBlasterMV header connection. The header is useful during prototyping because it allows you to verify or modify the Cyclone FPGA's contents. During production, you can remove the header to save cost. Program Flow The Jam Player provides an interface for manipulating the IEEE Std. 1149.1 JTAG TAP state machine. The TAP controller is a 16-state, state machine that is clocked on the rising edge of TCK, and uses the TMS pin to control JTAG operation in a device. Figure 13-20 shows the flow of an IEEE Std. 1149.1 TAP controller state machine. 13-32 Preliminary Altera Corporation May 2003 Configuration Schemes Figure 13-20. JTAG TAP Controller State Machine TMS = 1 TEST_LOGIC/ RESET TMS = 0 TMS = 1 TMS = 0 RUN_TEST/ IDLE SELECT_DR_SCAN TMS = 1 TMS = 1 SELECT_IR_SCAN TMS = 0 TMS = 0 TMS = 1 CAPTURE_DR TMS = 1 CAPTURE_IR TMS = 0 TMS = 0 SHIFT_DR TMS = 0 SHIFT_IR TMS = 0 TMS = 1 TMS = 1 EXIT1_DR TMS = 1 TMS = 1 EXIT1_IR TMS = 0 TMS = 0 PAUSE_DR PAUSE_IR TMS = 0 TMS = 1 TMS = 1 TMS = 0 TMS = 0 EXIT2_DR TMS = 0 EXIT2_IR TMS = 1 TMS = 1 TMS = 1 UPDATE_DR TMS = 1 UPDATE_IR TMS = 0 TMS = 0 While the Jam Player provides a driver that manipulates the TAP controller, the Jam Byte-Code File (.jbc) provides the high-level intelligence needed to program a given device. All Jam instructions that Altera Corporation May 2003 13-33 Preliminary Cyclone Device Handbook, Volume 1 send JTAG data to the device involve moving the TAP controller through either the data register leg or the instruction register leg of the state machine. For example, loading a JTAG instruction involves moving the TAP controller to the SHIFT_IR state and shifting the instruction into the instruction register through the TDI pin. Next, the TAP controller is moved to the RUN_TEST/IDLE state where a delay is implemented to allow the instruction time to be latched. This process is identical for data register scans, except that the data register leg of the state machine is traversed. The high-level Jam instructions are the DRSCAN instruction for scanning the JTAG data register, the IRSCAN instruction for scanning the instruction register, and the WAIT command that causes the state machine to sit idle for a specified period of time. Each leg of the TAP controller is scanned repeatedly, according to instructions in the .jbc file, until all of the target devices are programmed. Figure 13-21 illustrates the functional behavior of the Jam Player when it parses the .jbc file. When the Jam Player encounters a DRSCAN, IRSCAN, or WAIT instruction, it generates the proper data on TCK, TMS, and TDI to complete the instruction. The flow diagram shows branches for the DRSCAN, IRSCAN, and WAIT instructions. Although the Jam Player supports other instructions, they are omitted from the flow diagram for simplicity. 13-34 Preliminary Altera Corporation May 2003 Configuration Schemes Figure 13-21. Jam Player Flow Diagram (Part 1 of 2) Start Set TMS to 1 and Pulse TCK Five Times Test-Logic-Reset Set TMS to 0 and Pulse TCK Run-Test/Idle Switch WAIT Read Instruction from the Jam File Case[] DRSCAN IRSCAN Set TMS to 0 and Pulse TCK Run-Test/Idle Delay Parse Argument Parse Argument EOF? T F Set TMS to 1 and Pulse TCK Twice Select-IR-Scan Set TMS to 1 and Pulse TCK Select-DR-Scan Set TMS to 0 and Pulse TCK Twice Shift-DR Set TMS to 0 and Pulse TCK and Write TDI Shift-DR Set TMS to 1 and Pulse TCK Three Times Test-Logic-Reset Switch Set TMS to 0 and Pulse TCK Twice Shift-IR Set TMS to 0 and Pulse TCK and Write TDI Shift-IR End Set TMS to 1 and Pulse TCK Exit1-IR Set TMS to 0 and Pulse TCK Pause-IR Set TMS to 1 and Pulse TCK Twice Update-IR Set TMS to 0 and Pulse TCK Run-Test/Idle Switch T EOF Shift-IR F Set TMS to 0 and Pulse TCK and Write TDI Continued on Part 2 of Flow Diagram Altera Corporation May 2003 13-35 Preliminary Cyclone Device Handbook, Volume 1 Figure 13-22. Jam Player Flow Diagram (Part 2 of 2) Continued from Part 1 of Flow Diagram Compare Case[] Default Capture Set TMS to 1 and Pulse TCK and Store TDO Exit1-DR Loop< DR Length Set TMS to 1 and Pulse TCK and Store TDO Exit1-DR Set TMS to 0 and Pulse TCK Set TMS to 1 and Pulse TCK Update-IR Shift-DR T Set TMS to 0 and Pulse TCK, Write TDI, and Store TDO F Loop< DR Length T Set TMS to 0 and Pulse TCK, Write TDI, and Store TDO F Correct F TDO Value T Set TMS to 1 and Pulse TCK Report Error Set TMS to 1 and Pulse TCK and Store TDO Exit1-DR F Loop< DR Length Run-Test/Idle T Switch Set TMS to 1 and Pulse TCK Update-IR Set TMS to 0 and Pulse TCK and Write TDI Update-IR Set TMS to 0 and Pulse TCK Run-Test/Idle Set TMS to 0 and Pulse TCK Run-Test/Idle Switch Switch Execution of a Jam program starts at the beginning of the program. The program flow is controlled using GOTO, CALL/RETURN, and FOR/NEXT structures. The GOTO and CALL statements refer to labels that are symbolic names for program statements located elsewhere in the Jam program. The language itself enforces almost no constraints on the organizational structure or control flow of a program. 1 The Jam language does not support linking multiple Jam programs together or including the contents of another file into a Jam program. 13-36 Preliminary Altera Corporation May 2003 Configuration Schemes Jam Instructions Each Jam statement begins with one of the instruction names listed in Table 13-8. The instruction names, including the names of the optional instructions, are reserved keywords that you cannot use as variable or label identifiers in a Jam program. Table 13-8. Instruction Names BOOLEAN CALL CRC DRSCAN DRSTOP EXIT EXPORT FOR GOTO IF Note to Table 13-8: (1) This instruction name is an optional language extension. INTEGER IRSCAN IRSTOP LET NEXT NOTE POP POSTDR POSTIR PREDR PREIR PRINT PUSH RETURN STATE WAIT VECTOR (1) VMAP (1) - Table 13-9 shows the state names that are reserved keywords in the Jam language. These keywords correspond to the state names specified in the IEEE Std. 1149.1 JTAG specification. Table 13-9. Reserved Keywords (Part 1 of 2) IEEE Std. 1149.1 JTAG State Names Test-Logic-Reset Run-Test-Idle Select-DR-Scan Capture-DR Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR Select-IR-Scan Capture-IR Jam Reserved State Names RESET IDLE DRSELECT DRCAPTURE DRSHIFT DREXIT1 DRPAUSE DREXIT2 DRUPDATE IRSELECT IRCAPTURE Altera Corporation May 2003 13-37 Preliminary Cyclone Device Handbook, Volume 1 Table 13-9. Reserved Keywords (Part 2 of 2) IEEE Std. 1149.1 JTAG State Names Shift-IR Exit1-IR Pause-IR Exit2-IR Update-IR Jam Reserved State Names IRSHIFT IREXIT1 IRPAUSE IREXIT2 IRUPDATE Example Jam File that Reads the IDCODE The following illustrates the flexibility and utility of the Jam STAPL. The example code reads the IDCODE out of a single device in a JTAG chain. 1 The array variable, I_IDCODE, is initialized with the IDCODE instruction bits ordered the LSB first (on the left) to most significant bit (MSB) (on the right). This order is important because the array field in the IRSCAN instruction is always interpreted and sent, MSB to LSB. Example Jam File Reading IDCODE BOOLEAN read_data[32]; BOOLEAN I_IDCODE[10] = BIN 1001101000; `assumed BOOLEAN ONES_DATA[32] = HEX FFFFFFFF; INTEGER i; `Set up stop state for IRSCAN IRSTOP IRPAUSE; `Initialize device STATE RESET; IRSCAN 10, I_IDCODE[0..9]; `LOAD IDCODE INSTRUCTION STATE IDLE; WAIT 5 USEC, 3 CYCLES; DRSCAN 32, ONES_DATA[0..31], CAPTURE read_data[0..31]; `CAPTURE IDCODE PRINT "IDCODE:"; FOR i=0 to 31; PRINT read_data[i]; NEXT i; EXIT 0; 13-38 Preliminary Altera Corporation May 2003 Combining Configuration Schemes Combining Configuration Schemes This section shows you how to configure Cyclone FPGAs using multiple configuration schemes on the same board. Active Serial & JTAG You can combine the AS configuration scheme with JTAG-based configuration. Set the MSEL[1..0] pins to 00 in this setup, as shown in Figure 13-23. This setup uses two 10-pin download cable headers on the board. The first header programs the serial configuration device insystem via the AS programming interface, and the second header configures the Cyclone FPGA directly via the JTAG interface. If you try configuring the device using both schemes simultaneously, JTAG configuration takes precedence and AS configuration will be terminated. Altera Corporation May 2003 13-39 Preliminary Cyclone Device Handbook, Volume 1 Figure 13-23. Combining AS & JTAG Configuration (1) VCC VCC (1) VCC (1) 10 k Serial Configuration Device 10 k 10 k Cyclone FPGA nSTATUS N.C. CONF_DONE nCEO (2) nCONFIG 10 k nCE 10 k GND MSEL1 MSEL0 VCC VCC 10 k GND DATA DCLK nCS ASDI DATA DCLK nCSO ASDO TCK TDO TMS TDI MasterBlaster or ByteBlasterMV 10-Pin Male Header (top View) Pin 1 VCC (3) Pin 1 VCC (1) VIO (4) 10 k ByteBlaster II 10-Pin Male Header GND Notes to Figure 13-23: (1) (2) (3) (4) Connect these pull-up resistors to 3.3 V. The nCEO pin is left unconnected. You should connect the pull-up resistor to the same supply voltage as the download cable. VIO is a reference voltage for the MasterBlaster output driver. VIO should match the device's VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. Passive Serial & JTAG The PS- and JTAG-based configuration are also supported on the same board. Set the MSEL[1..0] pins to 01 in this setup. Figure 13-24 shows the pin connections required for configuring Cyclone FPGAs using PS and JTAG interfaces on the same board. The JTAG chain only connects to the Cyclone FPGA in Figure 13-24, but could also connect to the configuration device for in-system programming of that device. If you try configuring the device using both schemes simultaneously, JTAG configuration takes precedence and PS configuration will be terminated. 13-40 Preliminary Altera Corporation May 2003 Device Options Figure 13-24. Combining PS & JTAG Configuration VCC VCC 10 k VCC (1) VCC (1) VCC (1) 10 k Cyclone Device TCK TDO TMS TDI DCLK DATA0 nSTATUS CONF_DONE nCONFIG 10 k 10 k 10 k Configuration Device DCLK DATA OE nCS nINIT_CONF (2) VCC (5) MSEL0 MSEL1 GND nCEO nCE GND N.C. (3) ByteBlaster II, MasterBlaster, or ByteBlasterMV 10-Pin Male Header Pin 1 VCC (1) GND VIO (4) 10 k GND GND Notes to Figure 13-24: (1) The pull-up resistor should be connected to the same supply voltage as the configuration device. The EPC16, EPC8, EPC4, and EPC2 devices' OE and nCS pins have internal, user-configurable pull-up resistors. If you use internal pull-up resistors, do not use external pull-up resistors on these pins. The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices. If nINIT_CONF is not used, nCONFIG must be pulled to VCC through a resistor. The nCEO pin is left unconnected for the last device in the chain. VIO is a reference voltage for the MasterBlaster output driver. VIO should match the device's VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. Connect MSEL0 to the Vcc supply voltage of the I/O Bank it resides in. (2) (3) (4) (5) Device Options You can set Cyclone FPGA options in Altera's Quartus II development software using the Device & Pin Options dialog box. Select Compiler Settings (Processing menu), then click on the Chips & Devices tab. Figure 13-25 shows the Device & Pin Options dialog box. Altera Corporation May 2003 13-41 Preliminary Cyclone Device Handbook, Volume 1 Figure 13-25. Configuration Options Dialog Box 13-42 Preliminary Altera Corporation May 2003 Device Options Table 13-10 summarizes each of these options. Table 13-10. Cyclone Configuration Option Bits (Part 1 of 2) Device Option Auto-restart configuration on frame error Option Usage If a data error occurs during configuration, you can choose how to restart configuration. Default Configuration (Option Off) The configuration process stops until you direct the device to restart configuration. The nSTATUS pin is driven low when an error occurs. When nCONFIG is pulled low and then high, the device begins to reconfigure. Modified Configuration (Option On) The configuration process restarts automatically. The nSTATUS pin drives low and releases. The nSTATUS pin is then pulled to VCC by the pullup resistor, indicating that configuration can restart. In the configuration device scheme, if the target device's nSTATUS pin is tied to the configuration device's OE pin, the nSTATUS reset pulse resets the configuration device automatically. The configuration device then releases its OE pin (which is pulled high) and reconfiguration begins. If an error occurs during passive configuration, the device can be reconfigured without the system having to pulse nCONFIG. After nSTATUS goes high, reconfiguration can begin. Release clears before tri-states During configuration, the device I/O pins are tri-stated. During initialization, you choose the order for releasing the tri-states and clearing the registers. The device releases the tristates on its I/O pins before releasing the clear signal on its registers. The device releases the clear signals on its registers before releasing the tri-states. You can use this option to allow the design to operate before it drives out, so all outputs do not start up low. Chip-wide reset is enabled for all registers in the device. All registers are cleared when the DEV_CLRn pin is driven low. Enable chip-wide reset Enables a single pin to Chip-wide reset is not enabled. reset all device The DEV_CLRn pin is available registers. as a user I/O pin. Altera Corporation May 2003 13-43 Preliminary Cyclone Device Handbook, Volume 1 Table 13-10. Cyclone Configuration Option Bits (Part 2 of 2) Device Option Enable chip-wide output enable Option Usage Default Configuration (Option Off) Modified Configuration (Option On) Chip-wide output enable is enabled for all device tristates. After configuration, all user I/O pins are tri-stated when DEV_OE is low. The INIT_DONE signal is available on the open-drain INIT_DONE pin. This pin drives low during configuration. After initialization, it is released and pulled high externally. The INIT_DONE pin must be connected to a 10-k pull-up resistor. If the INIT_DONE output is used, the INIT_DONE pin cannot be used as a user I/O pin. The Quartus II software generates compressed programming files and Cyclone FPGAs decompress the bit stream during configuration. Enables a single pin to Chip-wide output enable is not control all device enabled. The DEV_OE pin is tri-states. available as a user I/O pin. Enable INIT_DONE output out a signal when the The INIT_DONE signal is not available. The INIT_DONE pin initialization process is is available as a user I/O pin. complete and the device has entered user mode. Enables a pin to drive Data Compression Enables Cyclone FPGAs to receive compressed configuration bit stream in Active and PS configuration schemes. The Quartus II software generates uncompressed programming files and Cyclone FPGAs do not decompress data. 13-44 Preliminary Altera Corporation May 2003 Device Configuration Pins Device Configuration Pins Table 13-11 summarizes the Cyclone FPGA configuration pins. Table 13-11. Pin Functions (Part 1 of 3) Pin Name MSEL1 MSEL0 - User Mode Configuration Scheme All Pin Type Input Description Two-bit configuration input. Sets the Cyclone device configuration scheme. After configuration, the Cyclone FPGA is not affected by logic levels on this pin. The device drives nSTATUS low immediately after power-up and releases it within 5 s. (When using a configuration device, the configuration device holds nSTATUS low for up to 200 ms.) The nSTATUS pin must be pulled up to VCC with a 10-k resistor. If an error occurs during configuration, nSTATUS is pulled low by the target device. If an external source drives the nSTATUS pin low during configuration or initialization, the target device enters an error state. Driving nSTATUS low after configuration and initialization does not affect the configured device. However, if a configuration device is used, driving nSTATUS low will cause that device to attempt to configure the Cyclone FPGA. Configuration control input. A low transition resets the target device; a low-to-high transition begins configuration. All I/O pins go tri-state when setting nCONFIG low. nSTATUS - All Bidirectional open-drain nCONFIG - All Input Altera Corporation May 2003 13-45 Preliminary Cyclone Device Handbook, Volume 1 Table 13-11. Pin Functions (Part 2 of 3) Pin Name CONF_DONE - User Mode Configuration Scheme All Pin Type Bidirectional open-drain Description Status output. The target device drives the CONF_DONE pin low before and during configuration. Once all configuration data is received without error and the initialization clock cycle starts, the target device releases CONF_DONE. Status input. After all data is received and CONF_DONE goes high, the target device initializes and enters user mode. The CONF_DONE pin must be pulled to VCC with a 10-k resistor. An external source can drive this pin low to delay the initialization process, except when configuring with a configuration device. Driving CONF_DONE low after configuration and initialization does not affect the configured device. DCLK - PS AS Input (PS) Output (AS) In PS configuration, the clock input clocks data from an external source into the target device. In AS configuration, DCLK is an output from the Cyclone FPGA that provides timing for the configuration interface. After configuration, the logic levels on this pin do not affect the Cyclone FPGA. Control signal from the Cyclone FPGA to the serial configuration device in AS mode used to read out configuration data. Control signal from the Cyclone FPGA to the serial configuration device in AS mode that enables the configuration device. Active-low chip enables. The nCE pin activates the device with a low signal to allow configuration and should be tied low for single device configuration. The nCE pin must be held low during configuration, initialization, and user mode. Output that drives low when device configuration is complete. During multi-device configuration, this pin feeds a subsequent device's nCE pin. Optional user-supplied clock input. Synchronizes the initialization of one or more devices. ASDO I/O AS Output nCSO I/O AS Output nCE - All Input nCEO I/O Multi-device Output CLKUSR I/O All Input 13-46 Preliminary Altera Corporation May 2003 Device Configuration Files Table 13-11. Pin Functions (Part 3 of 3) Pin Name DATA0 - User Mode Configuration Scheme Configuration device PS PPA FPP All Pin Type Input Description Data input. In serial configuration mode, bit-wide configuration data is presented to the target device on the DATA0 pin. INIT_DONE I/O Output open-drain Status pin. Can be used to indicate when the device has initialized and is in user mode. The INIT_DONE pin must be pulled to VCC with a 10-k ohm resistor. The INIT_DONE pin drives low during configuration. Before and after configuration, the INIT_DONE pin is released and is pulled to VCC by an external pull-up resistor. Because INIT_DONE is tri-stated before configuration, it is pulled high by the external pullup resistor. Thus, the monitoring circuitry must be able to detect a low-to-high transition. This option is set in the Quartus II software. Optional pin that allows the user to override all tristates on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as programmed. This option is set in the Quartus II software. Optional pin that allows you to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as programmed. This option is set in the Quartus II software. JTAG pins. JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. DEV_OE I/O All Input DEV_CLRn I/O All Input TDI TDO TMS TCK JTAG pins All Input Output Input Input Device Configuration Files The Quartus II software can create one or more configuration and programming files to support the configuration schemes discussed in this application note. This section describes these files. SRAM Object File (.sof) You should use an .sof during PS and JTAG configuration when the data is downloaded directly from the ByteBlaster II, MasterBlaster, or ByteBlasterMV download cables. For Cyclone FPGAs, the Quartus II Altera Corporation May 2003 13-47 Preliminary Cyclone Device Handbook, Volume 1 Compiler's Assembler module automatically creates the .sof file for each device in your design. The Quartus II software controls the configuration sequence and automatically inserts the appropriate headers into the configuration data stream. All other configuration files are created from the .sof. Programmer Object File (.pof) A .pof is used by the Altera programming hardware to program a configuration device, including serial configuration devices and enhanced configuration devices. A .pof is automatically generated when a Cyclone project is compiled for the configuration device selected in the Configuration dialog box. Raw Binary File (.rbf) The .rbf is a binary file (e.g., one byte of .rbf data is eight configured bits 10000101 (85 Hex)) containing the configuration data. Store data so that the LSB of each data byte is loaded first. A mass storage device can store the converted image. The microprocessor can then read data from the binary file and load it into device. You can also use the microprocessor to perform real-time conversion during configuration. In the PS configuration scheme, the data is shifted in serially, LSB first. Hexadecimal (Intel-Format) File (.hex) A .hex file is an ASCII file in the Intel hexidecimal format. Third-party programmers use this file to program Altera's serial configuration devices. Microprocessors can also use the .hex file to store and transmit configuration data using the PS configuration scheme. Tabular Text File (.ttf) The .ttf file is a tabular ASCII file that provides a comma-separated version of the configuration data for the bit-wide PS configuration scheme. In some applications, the storage device containing the configuration data is neither dedicated to nor connected directly to the target device. For example, a configuration device can also contain executable code for a system (e.g., BIOS routines) and other data. The .ttf allows you to include the configuration data as part of the microprocessor's source code using the include or source commands. The microprocessor can access this data from a configuration device or massstorage device and load it into the target device. A .ttf can be imported into nearly any assembly language or high-level language compiler. 13-48 Preliminary Altera Corporation May 2003 Configuration Reliability Jam File (.jam) A .jam file is an ASCII text file in the Jam device programming language that stores device programming information. These files are used to program, verify, and blank-check one or more devices in the Quartus II Programmer or in an embedded processor-type environment. Jam Byte-Code File (.jbc) A .jbc file is a binary version of a Jam file in a byte-code representation. The .jbc file stores device programming information used to program, verify, and blank-check one or more devices. Configuration Reliability The Cyclone architecture is designed to minimize the effects of power supply and data noise in a system, and to ensure that the configuration data is not corrupted during configuration or normal user-mode operation. A number of circuit design features ensure the highest possible level of reliability from this SRAM technology. Cyclic redundancy code (CRC) circuitry validates each data frame (i.e., sequence of data bits) as it is loaded into the target device. If the CRC generated by the device does not match the data stored in the data stream, the configuration process is halted, and the nSTATUS pin is pulled and held low to indicate an error condition. CRC circuitry ensures that noisy systems will not cause errors that yield an incorrect or incomplete configuration. The Cyclone FPGA architecture also provides a very high level of reliability in low-voltage brown-out conditions. Cyclone FPGA SRAM blocks require a certain VCC level to maintain accurate data. This voltage threshold is significantly lower than the voltage required to activate the device's POR circuitry. Therefore, the target device stops operating if the VCC starts to fail, and indicates an operation error by pulling and holding the nSTATUS pin low. You must then reconfigure the device before it can resume operation as a logic device. In active configuration schemes in which nCONFIG is tied to VCC, reconfiguration begins as soon as VCC returns to an acceptable level. The low pulse on nSTATUS resets the configuration device by driving OE low. In passive configuration schemes, the host system starts the reconfiguration process. These device features ensure that Cyclone FPGAs have the highest possible reliability in a wide variety of environments, and provide the same high level of system reliability that exists in other Altera PLDs. Altera Corporation May 2003 13-49 Preliminary Cyclone Device Handbook, Volume 1 Board Layout Tips Even though the DCLK signal (used in PS and AS configuration schemes) is fairly low-frequency, it drives edge-triggered pins on the Cyclone FPGA. Therefore, any overshoot, undershoot, ringing, or other noise can affect configuration. When designing the board, lay out the DCLK trace using the same techniques as laying out a clock line, including appropriate buffering. If more than five devices are used, Altera recommends using buffers to split the fan-out on the DCLK signal. 13-50 Preliminary Altera Corporation May 2003 14. Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet C51014-1.0 Features The serial configuration devices provide the following features: 1- and 4-Mbit flash memory devices that serially configure CycloneTM FPGAs Easy-to-use four-pin interface Low cost, low pin count and non-volatile memory Low current during configuration and near-zero standby mode current 3.3-V operation Available in 8-pin small outline integrated circuit (SOIC) package Enables the Nios processor to access unused flash memory through active serial (AS) memory interface Re-programmable memory with more than 100,000 erase/program cycles Programming support with ByteBlasterTM II download cable Additional programming support with the Altera Programming Unit (APU) and programming hardware from BP Microsystems, System General, and other vendors Software design support with the Altera Quartus II development system for Windows-based PCs as well as Sun SPARC station and HP 9000 Series 700/800 Delivered with the memory array erased (all the bits set to 1) Figure 14-1 shows the Altera serial configuration device 8-pin SOIC package and its pin-out diagram. Figure 14-1. Altera Serial Configuration Device Package Pin-Out Diagram EPCS1 or EPCS4 Device nCS DATA VCC GND 1 2 3 4 8 7 6 5 VCC VCC DCLK ASDI 1 Whenever the term "serial configuration device(s)" is used in this document, it refers to Altera EPCS1 and EPCS4 devices. Altera Corporation May 2003 14-1 Preliminary Cyclone Device Handbook, Volume 1 Functional Description With SRAM-based devices such as Cyclone FPGAs, configuration data must be reloaded each time the system initializes, or when a new configuration is needed. Serial configuration devices are flash memory devices with a serial interface that can store configuration data for a Cyclone device and reload the data to the device upon power-up or reconfiguration. Table 14-1 lists the serial configuration devices. Table 14-1. Serial Configuration Devices (3.3-V Operation) Device EPCS1 EPCS4 Memory Size (Bits) 1,048,576 4,194,304 Table 14-2 lists the serial configuration device used with each Cyclone FPGA and the configuration file size. Table 14-2. Serial Configuration Device for Cyclone Devices Cyclone Device EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 Note to Table 14-2: (1) These are preliminary, uncompressed file sizes. Configuration File Size (Mbits) (1) 0.628 0.925 1.167 2.324 3.559 Serial Configuration Device EPCS1 v v v EPCS4 v v v v v With the new data-decompression feature in the Cyclone FPGA family, designers can use smaller serial configuration devices to configure larger Cyclone FPGAs. Serial configuration devices cannot be cascaded. f See Chapter 13, Configuring Cyclone FPGAs for more information regarding the Cyclone FPGA decompression feature in AS mode. The serial configuration devices are designed to configure Cyclone FPGAs and cannot configure other existing device families. Figure 14-2 shows the serial configuration device block diagram. 14-2 Preliminary Altera Corporation May 2003 Accessing Memory in Serial Configuration Devices Figure 14-2. Serial Configuration Device Block Diagram Serial Configuration Device nCS DCLK Control Logic DATA I/O Shift Register ASDI Address Counter Data Buffer Status Register Decode Logic Memory Array Accessing Memory in Serial Configuration Devices A designer can access the unused memory locations of the serial configuration device through the Nios processor and SOPC Builder to store/retrieve data or configuration files. SOPC Builder is an Altera tool for creating bus-based (especially microprocessor-based) systems in Altera devices. SOPC Builder assembles library components like processors and memories into custom microprocessor systems. SOPC Builder includes an interface core specifically for the serial configuration device. Using this core, a designer can create a system with a Nios embedded processor that allows software access to any memory location within the serial configuration device. For more information on accessing memory within the serial configuration device, contact Altera Applications. f Altera Corporation May 2003 14-3 Preliminary Cyclone Device Handbook, Volume 1 Pin Description As shown in Figure 14-1, the serial configuration device is an 8-pin device. The control pins on the serial configuration device are: serial data output (DATA), active serial data input (ASDI), serial clock (DCLK), and chip select (nCS). Table 14-3 shows the serial configuration device's pin descriptions. Table 14-3. Serial Configuration Device Pin Description Pin Name DATA Pin Number 2 Pin Type Output Description DATA output signal transfers the data serially out of the serial configuration device into the Cyclone FPGA during read/configuration operation. During a read/configuration operation, the serial configuration device is enabled by pulling nCS low. The DATA signal transitions on the falling edge of DCLK. Active serial data input signal is used to transfer data serially into the serial configuration device. It receives the data that should be programmed into the serial configuration device. Values register on the rising edge of DCLK. Active low chip select input signal toggles at the beginning and end of a valid instruction. When this signal is high, the device is deselected and the DATA signal is tri-stated. When the signal is low, it enables the device and puts the device in an active mode. After power up, the serial configuration device requires a falling edge on the nCS signal before beginning any operation. ASDI 5 Input nCS 1 Input DCLK 6 Input DCLK is provided by the Cyclone FPGA. This signal provides the timing of the serial interface. The data presented at ASDI are latched in to the serial configuration device, at the rising edge of DCLK. Data on the DATA pin changes after the falling edge of DCLK and is latched into the Cyclone FPGA on the rising edge. Power pins connect to 3.3 V. Ground pin. VCC GND 3, 7, 8 4 Power Ground Programming & Configuration File Support The Quartus II design software provides programming support for serial configuration devices. After selecting the serial configuration device, the Quartus II software automatically generates the Programmer Object File (.pof) to program the device. The software allows users to select the appropriate serial configuration device density that most efficiently stores the configuration data for a selected Cyclone FPGA. Serial configuration devices are programmed using the APU with the appropriate programming adapter (PLMSEPC-8) via the Quartus II software or the ByteBlaster II download cable via the Quartus II software. In addition, many third-party programmers, such as BP Microsystems and System General, offer programming hardware that supports serial configuration devices. 14-4 Preliminary Altera Corporation May 2003 Programming & Configuration File Support During in-system programming of a serial configuration device via the ByteBlaster II download cable, the cable pulls nCONFIG low to reset the Cyclone device and overrides the 10-k pull-down resistors on the Cyclone device's nCE pin (see Figure 14-5). The download cable then uses the four interface pins (DATA, nCS, ASDI, and DCLK) to program the serial configuration device memory. Once the programming is complete, the download cable releases the serial configuration device's four interface pins and the Cyclone device's nCE pin, and pulses nCONFIG to start configuration. Figure 14-3 shows the timing waveform for write operation to the serial configuration device. Figure 14-3. Write Operation Timing tCSH nCS tNCSH DCLK tDSU ASDI Bit n tDH Bit n - 1 Bit 0 tNCSSU tCH tCL DATA High Impedance Table 14-4 defines the serial configuration device timing parameters for write operation. Table 14-4. Write Operation Parameters (Part 1 of 2) Symbol fWCLK Parameter Write clock frequency (from Cyclone FPGA or ByteBlaster II cable) Min Max 20 Unit MHz tCH tCL tNCSSU tNCSH tDSU DCLK high time DCLK low time Chip select (nCS) setup time Chip select (nCS) hold time Data (ASDI) in setup time before rising edge on DCLK 25 25 10 10 5 ns ns ns ns ns Altera Corporation May 2003 14-5 Preliminary Cyclone Device Handbook, Volume 1 Table 14-4. Write Operation Parameters (Part 2 of 2) Symbol tDH tCSH Parameter Data (ASDI) hold time after rising edge on DCLK Chip select high time Min 5 100 Max Unit ns ns Figure 14-4 shows the timing waveform for the serial configuration device's read operation. Figure 14-4. Read Operation Timing nCS tCH DCLK tnCLK2D DATA Bit N Bit N - 1 tCL Bit 0 tODIS ASDI Add_Bit 0 Table 14-5 defines the serial configuration device timing parameters for read operation. Table 14-5. Read Operation Parameters Symbol fRCLK tCH tCL tODIS tnCLK2D Parameter Read clock frequency (from Cyclone FPGA) Min Max 20 Unit MHz ns ns DCLK high time DCLK low time Output disable time after read Clock falling edge to data 25 25 15 15 ns ns f For more information on programming and configuration support, see the following documents: Altera Programming Hardware Data Sheet Programming Hardware Manufacturers ByteBlaster II Parallel Port Download Cable Data Sheet 14-6 Preliminary Altera Corporation May 2003 Cyclone FPGA Configuration Cyclone FPGA Configuration Cyclone FPGAs can be configured with a serial configuration device through AS configuration mode. There are four signals on the serial configuration device that interface directly with the Cyclone device's control signals. The serial configuration device signals DATA, DCLK, ASDI, and nCS interface with DATA0, DCLK, ASDO, and nCSO control signals on a Cyclone FPGA, respectively. Figure 14-5 shows a serial configuration device programmed via a download cable configuring a Cyclone FPGA in AS mode. Figure 14-6 shows a serial configuration device programmed using the APU or a third-party programmer configuring a Cyclone FPGA in AS configuration mode. Figure 14-5. Cyclone Configuration in AS Mode (Serial Configuration Device Programmed Using Download Cable) VCC (1) 10 k VCC (1) VCC (1) 10 k Cyclone FPGA CONF_DONE nSTATUS Serial Configuration Device (2) 10 k DATA DCLK nCS ASDI DATA0 DCLK nCSO ASDO nCONFIG 00 nCEO 10 k nCE MSEL[1..0] (3) Pin 1 VCC (1) Altera Corporation May 2003 14-7 Preliminary Cyclone Device Handbook, Volume 1 Figure 14-6. Cyclone Configuration in AS Mode (Serial Configuration Device Programmed by APU or ThirdParty Programmer) VCC (1) 10 k VCC (1) VCC (1) 10 k Cyclone FPGA CONF_DONE nSTATUS Serial Configuration Device (2) nCONFIG 00 nCEO 10 k nCE MSEL[1..0] (3) DATA DCLK nCS ASDI DATA0 DCLK nCSO ASDO Notes to Figures 14-5 and 14-6: (1) (2) (3) VCC = 3.3-V. Serial configuration devices cannot be cascaded. Set MSEL0 to 0 and MSEL1 to 0 for AS configuration mode. The Cyclone FPGA acts as the configuration master in the configuration flow and provides the DCLK to the serial configuration device. The Cyclone device enables the serial configuration device by pulling the nCS signal low via the nCSO signal (See Figures 14-5 and 14-6). Consequently, the Cyclone FPGA sends the instructions and addresses to the serial configuration device via the ASDO signal. The serial configuration device responds to the instructions by sending the configuration data to the Cyclone FPGA's DATA0 pin on the falling edge of DCLK. The data is latched into the Cyclone device's DCLK signal's rising edge. The Cyclone FPGA controls the nSTATUS and CONF_DONE pins during configuration in AS mode. If the CONF_DONE signal does not go high at the end of configuration or if the signal goes high too early, the Cyclone FPGA will pulse its nSTATUS pin low to start reconfiguration. Upon successful configuration, the Cyclone FPGA releases the CONF_DONE pin, allowing the external 10-k resistor to pull this signal high. Initialization begins after the CONF_DONE goes high and completes within 136 clock cycles. After initialization, the Cyclone FPGA enters user mode. f For more information on configuring Cyclone FPGAs in AS mode or other configuration modes, see Chapter 13, Configuring Cyclone FPGAs. Altera Corporation May 2003 14-8 Preliminary Cyclone FPGA Configuration Serial configuration devices cannot be cascaded. Therefore, when a design requires multiple Cyclone FPGAs, the Cyclone FPGAs are configured by a single serial configuration device. Check Table 14-1 to ensure the programming file size of the cascaded Cyclone FPGAs does not exceed the capacity of a serial configuration device. Designers can choose any serial configuration device according to the system requirements. Figure 14-7 shows the AS configuration scheme with multiple Cyclone FPGAs in the chain. In AS configuration mode, all the devices in the chain must be Cyclone devices. Figure 14-7. Multiple Devices in AS Mode VCC (1) 10 k VCC (1) 10 k VCC (1) 10 k Cyclone FPGA (Master) (2) CONF_DONE nSTATUS Serial Configuration Device (3) nCONFIG Cyclone FPGA (Slave) (2) CONF_DONE nSTATUS nCONFIG nCE nCEO MSEL[1..0] 00 nCE nCEO MSEL[1..0] 01 (4) DATA0 DCLK (5 ) DATA DCLK nCS ASDI DATA0 DCLK nCSO ASDO Notes to Figure 14-7: (1) (2) (3) (4) (5) VCC = 3.3-V. In AS mode, the first Cyclone device in the chain is the master device. The other Cyclone devices in the chain are slave devices and must be in passive serial (PS) configuration mode. Serial configuration devices cannot be cascaded. Set MSEL0 to 0 and MSEL1 to 0 to select AS mode in the Cyclone device. Set MSEL0 to 0 and MSEL1 to 1 to select PS mode in the Cyclone device. Altera Corporation May 2003 14-9 Preliminary Cyclone Device Handbook, Volume 1 Figure 14-8 shows the timing waveform for Cyclone FPGA AS configuration scheme using a serial configuration device. Figure 14-8. AS Configuration Timing tPOR nCONFIG nSTATUS CONF_DONE nCSO tCL DCLK tH ASDO Read Address tSU DATA0 bit N bit N - 1 bit 1 bit 0 136 Cycles INIT_DONE tCH User I/O User Mode Table 14-6 shows the timing parameters for AS configuration mode. Table 14-6. Timing Parameters for AS Configuration Symbol fCLK tCH tCL tH tSU tPOR Parameter DCLK frequency (from Cyclone FPGA) DCLK high time DCLK low time Data hold time after rising edge on DCLK Data set up time before rising edge on DCLK POR delay Min Typ 15 Max 20 Unit MHz ns ns ns ns 25 25 0 5 100 ms 14-10 Preliminary Altera Corporation May 2003 Power & Operation Power & Operation This section describes the power modes, power-on reset (POR) delay, error detection, and initial programming state of serial configuration devices. Power Mode Serial configuration devices support active power and standby power modes. When nCS is low, the device is enabled and is in active power mode. The Cyclone FPGA is configured while in active power mode. When nCS is high, the device is disabled but could remain in active power mode until all internal cycles have completed (such as program or erase operations). The serial configuration device then goes into stand-by power mode. The ICC1 parameter specifies the VCC supply current when the device is in active power mode and the ICC0 parameter specifies the current when the device is in stand-by power mode (see Table 14-10). Power-On Reset During initial power-up, a POR delay occurs to help stabilize the system voltage levels. In AS configuration, the Cyclone FPGA controls the configuration and has a longer POR delay than the serial configuration device. Therefore, the POR delay is governed by the Cyclone FPGA (typically 100 ms). Error Detection In AS configuration with the serial configuration device, the Cyclone FPGA monitors the configuration status through the nSTATUS and CONF_DONE pins. If an error condition occurs (nSTATUS driven low) or if the CONF_DONE pin does not go high, the Cyclone FPGA will initiate reconfiguration by pulsing the nSTATUS and nCSO signals, which controls the chip select pin on the serial configuration device (nCS). After an error, configuration automatically restarts if the Auto-Restart Upon Frame Error option is turned on in the Quartus II software. Altera Corporation May 2003 14-11 Preliminary Cyclone Device Handbook, Volume 1 Operating Conditions Tables 14-7 through 14-11 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for serial configuration devices. Table 14-7. Absolute Maximum Ratings Symbol VCC VI IMAX IOUT PD TSTG TAMB TJ Note (1) Condition With respect to ground With respect to ground Parameter Supply voltage DC input voltage DC VCC or GND current DC output current per pin Power dissipation Storage temperature Ambient temperature Junction temperature No bias Min -0.6 -0.6 -25 -65 -65 Max 4.0 4.0 15 25 54 150 135 135 Unit V V mA mA mW C C C Under bias Under bias Table 14-8. Recommended Operating Conditions Symbol VCC VI VO TA tR tF Parameter Supply voltage Input voltage Output voltage Operating temperature (2) Conditions Min 3.0 -0.3 0 Max 3.6 0.3 + VCC VCC 70 85 5 5 Unit V V V C C ns ns Respect to GND For commercial use For industrial use 0 -40 Input rise time Input fall time Table 14-9. DC Operating Conditions Symbol VIH VIL VOH VOL II IOZ Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input leakage current Tri-state output off-state current Conditions Min 0.7 x VCC -0.5 Max VCC + 0.4 0.3 x VCC Unit V V V IOH = -100 A (3) IOL = 1.6 mA (3) VI = VCC or GND VO = VCC or GND VCC - 0.2 0.4 -10 -10 10 10 V A A 14-12 Preliminary Altera Corporation May 2003 Package Table 14-10. ICC Supply Current Symbol ICC0 ICC1 Parameter VCC supply current (standby) VCC supply current (during active power mode) Conditions Min Max 50 Unit A mA 5 14 Table 14-11. Capacitance Symbol CIN COUT (1) (2) (3) (4) Note (4) Conditions VIN = 0 V VOUT = 0 V Parameter Input pin capacitance Output pin capacitance Min Max 6 8 Unit pF pF Notes to Table 14-7 through 14-11: See the Operating Requirements for Altera Devices Data Sheet. Maximum VCC rise time is 100 ms. The IOH parameter refers to high-level TTL or CMOS output current; the I OL parameter refers to low-level TTL or CMOS output current. Capacitance is sample-tested only at TA = 25 C and at a 20-MHz frequency. Package f All serial configuration devices are available in 8-pin plastic SOIC package. Figure 14-9 shows the mechanical drawing and specifications for this package. For more information on Altera device packaging, see Chapter 6, Package Information for Cyclone Devices. Altera Corporation May 2003 14-13 Preliminary Cyclone Device Handbook, Volume 1 Figure 14-9. 8-Pin SOIC Serial Configuration Device Package N Notes (1), (2) HE Pin 1 D h x 45 o Seating Plane A A1 e B Notes to Figure 14-9: (1) (2) All dimensions and tolerances conform to ANSI Y14.5M - 1982. JEDEC reference MS-013 option AE. 8 L Symbol A A1 B C D E e H h L N Min. _ _ _ _ _ _ _ _ _ _ C Dimentions (mm) Nom. 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BSC 5.80 0.25 0.40 8 o 0C Max. 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 0.90 8C o 8 Ordering Code Table 14-12 shows the ordering codes for serial configuration devices. Table 14-12. Serial Configuration Device Ordering Codes Device EPCS1 EPCS4 EPCS1SI8 EPCS4SI8 Ordering Code 14-14 Preliminary Altera Corporation May 2003 Index 1.5-V Devices Board Layout 12-21 Choose a Regulator Type 12-9 Designing with 12-1 Linear Voltage Regulators 12-4 Maximum Output Current 12-8 Power Sequencing & Hot Socketing 12-1 Regulator Application Examples 12-19 Regulator Circuits 12-10 Selecting Voltage Regulators 12-8 Split-Plane Method 12-23 Switching Voltage Regulators 12-6 Synchronous Switching Regulator Example 12-20 Using MultiVolt I/O Pins 12-2 Voltage Divider Network 12-10 Voltage Regulators 12-3 A Architecture addnsub Signal 2-7 Bus Hold 2-51 Byte Enables 2-23 Carry-Select Chain 2-10 Clear & Preset Logic Control 2-12 Clock Clock Feedback 2-37 Clock Mode Independent 2-25 Input/Output 2-25 Read/Write 2-27 Clock Multiplication & Division 2-35 Dual-Purpose Clock Pins 2-30 External Clock Inputs 2-36 External Clock Outputs 2-36 Global Clock Network 2-29 Global Clock Network & Phase-Locked Loops 2-29 Maximum Input & Output Clock Rates 4-27 Phase Shifting 2-37 Combined Resources 2-31 Configuration 3-5 Schemes 3-6 Testing 3-1 Control Signals 2-38 Control Signals & M4K Interface 2-23 Cyclone Architecture 2-1 DC & Switching Characteristics 4-1 Device Pin-Outs 5-1 Dynamic Arithmetic Mode 2-9 Embedded Memory 2-18 Functional Description 2-1 I/O Standard Advanced I/O Standard Support 2-52 External I/O Delay Parameters 4-21 I/O Structure 2-39 LVDS I/O Pins 2-54 MultiVolt I/O Interface 2-54 IEEE Std. 1149.1 (JTAG) Boundary Scan Support 3-1 LAB Control Signals 2-4 Interconnects 2-3 Lock Detect Signal 2-37 Logic Array Blocks 2-3 Logic Elements 2-5 Operating Modes 2-7 LUT Chain & Register Chain 2-7 Memory Configuration Sizes 2-21 DDR SDRAM & FCRAM 2-46 External RAM Interfacing 2-46 Modes 2-18 MultiTrack Interconnect 2-12 Normal Mode 2-8 Open-Drain Output 2-50 Operating Conditions 4-1 Operating Modes 3-6 Altera Corporation Index-1 Preliminary Cyclone FPGA Device Handbook Ordering Information 5-1 Parity Bit Support 2-20 PLLs 2-32 Power Consumption 4-8 Power Sequencing & Hot Socketing 2-55 Programmable Drive Strength 2-49 Programmable Duty Cycle 2-38 Programmable Pull-Up Resistor 2-51 Reference & Ordering Information 5-1 Shift Register Support 2-20 SignalTap II Embedded Logic Analyzer 3-5 Single-Port Mode 2-28 Slew-Rate Control 2-50 Software 5-1 Timing External Timing Parameters 4-14 Internal Timing Parameters 4-10 Model 4-9 Preliminary & Final 4-9 C Configuration Active Serial & JTAG 13-39 Active Serial Configuration (Serial Configuration Devices) 13-7 Combining Configuration Schemes 13-39 Configuring Cyclone FPGAs 13-1 FPGAs with JRunner 13-31 FPGAs with the MicroBlaster Software 13-23 Configuring Multiple Cyclone FPGAs 13-16 Configuring Multiple Devices (Cascading) 13-9 Connecting the JTAG Chain to the Embedded Processor 13-30 Data Compression 13-3 Device Configuration Overview 13-1 Device Configuration Files 13-47 Device Options 13-41 Jam Example Jam File that Reads the IDCODE 13-38 Instructions 13-37 STAPL 13-32 JTAG Configuration of Multiple Devices 13-28 JTAG Configuration Using a Download Cable 13-26 JTAG-Based Configuration 13-25 Passive Serial 13-13 Passive Serial & JTAG 13-40 Program Flow 13-32 Programming Configuration Devices 13-17 Programming Serial Configuration Devices 13-11 PS Configuration from a Microprocessor 13-22 PS Configuration Using a Download Cable 13-18 PS Configuration using Configuration Device 13-13 Quartus II Software Board Layout Tips 13-50 Configuration Reliability 13-49 Hexadecimal (Intel-Format) File (.hex) 13-48 Jam Byte-Code File (.jbc) 13-49 Jam File (.jam) 13-49 Programmer Object File (.pof) 13-48 Raw Binary File (.rbf) 13-48 SRAM Object File (.sof) 13-47 Tabular Text File (.ttf) 13-48 Schemes 13-6 Timing Passive Serial Timing 13-23 D Device Configuration Pins 13-45 I I/O Standards 11-1 1.5-V LVCMOS Normal & Wide Voltage Ranges (EIA/JEDEC Standard JESD811) 8-5 Index-2 Preliminary Altera Corporation 1.8-V LVCMOS Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD87) 8-4 LVTTL Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD87) 8-4 2.5-V LVCMOS Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD85) 8-4 LVTTL Normal & Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD85) 8-3 3.3-V (PCI Special Interest Group (SIG) PCI Local Bus Specification Revision 2.2) 8-5 LVCMOS (EIA/JEDEC Standard JESD8B) 8-3 LVTTL (EIA/JEDEC Standard JESD8B) 8-2 Bidirectional Pads 8-14 Cyclone I/O Banks 8-8 DC Guidelines 8-16 Differential I/O Standard Termination 8-13 Differential Pad Placement Guidelines 8-13 Differential SSTL-2 - EIA/JEDEC Standard JESD8-9A 8-8 Hot Socketing 8-12 I/O Termination 8-12 Input Pads 8-14 LVDS (ANSI/TIA/EIA Standard ANSI/TIA/EIA-644) 8-7 Output Pads 8-14 Pad Placement & DC Guidelines 8-13 Programmable Current Drive Strength 8-11 Quartus II Software Assigning Pins 8-18 Auto Placement & Verification of Selectable I/O Standards 8-20 Compiler Settings 8-17 Device & Pin Options 8-17 I/O Banks in the Floorplan View 8-19 Programmable Drive Strength Settings 8-19 Software Support 8-17 SSTL-2 Class I & II (EIA/JEDEC Standard JESD8-9A) 8-6 SSTL-3 Class I & II (EIA/JEDEC Standard JESD8-8) 8-5 Supported I/O Standards 8-2 Using Selectable I/O Standards in Cyclone Devices 8-1 Voltage-Referenced I/O Standard Termination 8-13 Voltages 5.0-V Device Compatibility 11-3 Devices Can Be Driven before PowerUp 11-6 Hot-Socketing 11-6 I/O Pins Remain Tri-Stated during PowerUp 11-6 MultiVolt I/O Operation 11-2 Power-On Reset 11-7 Power-Up Sequence 11-7 Signal Pins Do Not Drive the VCCIO or VCCINT Power Supplies 11-6 VREF Pad Placement Guidelines 8-13 L LVDS Clock Domains 9-3 Cyclone I/O Banks 9-1 Cyclone I/O Interface 9-3 Cyclone Receiver & Transmitter Termination 9-8 Implementing LVDS in Cyclone Devices 9-1 Quartus II Software Board Design Considerations 9-17 Capturing Serial Data on Cyclone LVDS Inputs 9-14 Design Guidelines 9-16 Differential Pad Placement Guidelines 9-17 Implementing Cyclone LVDS I/O Pins in the Quartus II Software 9-10 Receiver Circuit 9-15 Transmitter Circuit 9-13 Transmitting Serial Data on Cyclone LVDS Outputs 9-10 Receiver & Transmitter 9-4 Altera Corporation Index-3 Preliminary Cyclone FPGA Device Handbook Timing in Cyclone Devices 9-7 M Memory Bidirectional Double Data Rate 10-3 DDR Memory Support 10-4 Double Data Rate Input 10-1 Output 10-2 Implementing Double Data Rate I/O Signaling in Cyclone Devices 10-1 P PLL altpll Compilation Report 6-31 Input Ports 6-22 MegaWizard Customization 6-23 MegaWizard Page Description 6-25 Output Ports 6-23 Simulation 6-37 Timing Analysis 6-33 areset 6-12 Board Layout 6-17 Clock Combined Sources 6-41 Dedicated Clock Input Pins 6-40 Dual-Purpose Clock I/O Pins 6-40 External Clock Output 6-11 Feedback Modes 6-13 Global Clock Network 6-38 Multiplication & Division 6-8 Control Signals 6-12 Cyclone PLL Blocks 6-2 Hardware Features 6-8 Hardware Overview 6-1 Jitter Considerations 6-19 Modes No Compensation 6-15 Normal 6-13 Zero Delay Buffer 6-14 Partitioned VCCA Island within VCCINT Plane 6-17 pfdena 6-12 Phase Shifting 6-9 Pins 6-16 Pins & Clock Network Connections 6-6 pllena 6-12 Programmable Duty Cycle 6-10 Quartus II altpll Megafunction 6-21 Separate VCCA Power Plane 6-17 Software Support 6-21 Specifications 6-20 Thick VCCA Traces 6-18 Using PLLs in Cyclone Devices 6-1 VCCA & GNDA 6-17 S Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet 14-1 Accessing Memory 14-3 Cyclone FPGA Configuration 14-7 Error Detection 14-11 Features 14-1 Functional Description 14-2 Operating Conditions 14-12 Ordering Code 14-14 Package 14-13 Pin Description 14-4 Power & Operation 14-11 Power Mode 14-11 Power-On Reset 14-11 Programming & Configuration File Support 14-4 Software Overview 6-4 U Using Cyclone Devices in Multiple-Voltage Systems 11-1 Index-4 Preliminary Altera Corporation Cyclone Device Handbook, Volume 2 Preliminary Information 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com C5V2-1.0 Copyright (c) 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Printed on recycled paper ii Preliminary Altera Corporation Contents Chapter Revision Dates .......................................................................... iii About this Handbook ............................................................................. xiii How to Find Information ..................................................................................................................... xiii How to Contact Altera .......................................................................................................................... xiii Typographic Conventions .................................................................................................................... xiv Section I. PCB Layout Guidelines Revision History ....................................................................................................................... Section I-1 Chapter 1. Cyclone EP1C3T100 Device Pin Information Introduction ............................................................................................................................................ 1-1 Pin List ..................................................................................................................................................... 1-2 Pin Definitions ........................................................................................................................................ 1-7 PLL & Bank Diagram .......................................................................................................................... 1-10 Chapter 2. Cyclone EP1C3T144 Device Pin Information Introduction ............................................................................................................................................ 2-1 Pin List ..................................................................................................................................................... 2-2 Pin Definitions ........................................................................................................................................ 2-9 PLL & Bank Diagram .......................................................................................................................... 2-13 Chapter 3. Cyclone EP1C6 Device Pin Information Introduction ............................................................................................................................................ 3-1 Pin List ..................................................................................................................................................... 3-2 Pin Definitions ...................................................................................................................................... 3-16 PLL & Bank Diagram .......................................................................................................................... 3-20 Chapter 4. Cyclone EP1C12 Device Pin Information Introduction ............................................................................................................................................ 4-1 Pin List ..................................................................................................................................................... 4-2 Pin Definitions ...................................................................................................................................... 4-20 PLL & Bank Diagram .......................................................................................................................... 4-24 Chapter 5. Cyclone EP1C20 Device Pin Information Introduction ............................................................................................................................................ 5-1 Pin List ..................................................................................................................................................... 5-2 Altera Corporation v Preliminary Cyclone Device Handbook, Volume 2 Pin Definitions ...................................................................................................................................... 5-22 PLL & Bank Diagram .......................................................................................................................... 5-26 Chapter 6. Package Information for Cyclone Devices Introduction ............................................................................................................................................ 6-1 Device & Package Cross Reference ..................................................................................................... 6-1 Thermal Resistance ................................................................................................................................ 6-2 Package Outlines ................................................................................................................................... 6-2 100-Pin Plastic Thin Quad Flat Pack (TQFP) ................................................................................ 6-3 144-Pin Plastic Thin Quad Flat Pack (TQFP) ................................................................................ 6-5 240-Pin Plastic Quad Flat Pack (PQFP) ......................................................................................... 6-7 256-Pin Non-Thermally Enhanced FineLine Ball-Grid Array ................................................... 6-9 324-Pin Non-Thermally Enhanced FineLine Ball-Grid Array ................................................. 6-11 400-Pin Non-Thermally Enhanced FineLine Ball-Grid Array ................................................. 6-13 Chapter 7. Designing with FineLine BGA Packages Introduction ............................................................................................................................................ 7-1 Overview of BGA Packages ................................................................................................................. 7-1 PCB Layout Terminology ..................................................................................................................... 7-2 Escape Routing ................................................................................................................................. 7-2 Multi-Layer PCBs ............................................................................................................................. 7-2 Vias ..................................................................................................................................................... 7-2 Via Capture Pad ............................................................................................................................... 7-4 Surface Land Pad .............................................................................................................................. 7-4 Stringer ............................................................................................................................................... 7-5 PCB Layout for FineLine BGA Packages ........................................................................................... 7-6 Surface Land Pad Dimension ......................................................................................................... 7-6 Via Capture Pad Layout & Dimension ......................................................................................... 7-7 Signal Line Space & Trace Width ................................................................................................. 7-10 Number of PCB Layers .................................................................................................................. 7-11 Conclusion ............................................................................................................................................ 7-12 1-vi Preliminary Altera Corporation Chapter Revision Dates The chapters in this book, Cyclone Device Handbook, Volume 2, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. Cyclone EP1C3T100 Device Pin Information Revised: May 2003 Part number: C52001-1.0 Chapter 2. Cyclone EP1C3T144 Device Pin Information Revised: May 2003 Part number: C52002-1.0 Chapter 3. Cyclone EP1C6 Device Pin Information Revised: May 2003 Part number: C52003-1.0 Chapter 4. Cyclone EP1C12 Device Pin Information Revised: May 2003 Part number: C52004-1.0 Chapter 5. Cyclone EP1C20 Device Pin Information Revised: May 2003 Part number: C52005-1.0 Chapter 6. Package Information for Cyclone Devices Revised: May 2003 Part number: C52006-1.0 Chapter 7. Designing with FineLine BGA Packages Revised: May 2003 Part number: C52007-1.0 Altera Corporation iii Preliminary Cyclone Device Handbook, Volume 2 1-iv Preliminary Altera Corporation About this Handbook This handbook provides comprehensive information about the Altera(R) Cyclone family of devices. How to Find Information You can find more information in the following ways: The Adobe Acrobat Find feature, which searches the text of a PDF document. Click the binoculars toolbar icon to open the Find dialog box. Acrobat bookmarks, which serve as an additional table of contents in PDF documents. Thumbnail icons, which provide miniature previews of each page, provide a link to the pages. Numerous links, shown in green text, which allow you to jump to related information. How to Contact Altera Information Type Technical support For the most up-to-date information about Altera products, go to the Altera world-wide web site at www.altera.com. For technical support on this product, go to www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below. USA & Canada www.altera.com/mysupport/ (800) 800-EPLD (3753) (7:00 a.m. to 5:00 p.m. Pacific Time) All Other Locations altera.com/mysupport/ (408) 544-7000 (1) (7:00 a.m. to 5:00 p.m. Pacific Time) www.altera.com lit_req@altera.com (1) (408) 544-7000 (7:30 a.m. to 5:30 p.m. Pacific Time) ftp.altera.com Product literature Altera literature services Non-technical customer service FTP site Note to table: (1) www.altera.com lit_req@altera.com (1) (800) 767-3753 ftp.altera.com You can also contact your local Altera sales office or sales representative. Altera Corporation xiii Preliminary Cyclone Device Handbook, Volume 2 Typographic Conventions Visual Cue Bold Type with Initial Capital Letters bold type This document uses the typographic conventions shown below. Meaning Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file. Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design. Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: Italic Type with Initial Capital Letters Italic type Initial Capital Letters "Subheading Title" Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: "Typographic Conventions." Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier. Courier type 1., 2., 3., and a., b., c., etc. v 1 r f Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets are used in a list of items when the sequence of the items is not important. The checkmark indicates a procedure that consists of one step only. The hand points to information that requires special attention. The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. * 1-xiv Preliminary Altera Corporation Section I. PCB Layout Guidelines This section provides information for board layout designers to successfully layout their boards for Cyclone devices. It contains the required PCB layout guidelines, device pin tables, and package specifications. This section includes the following chapters: Chapter 1. Cyclone EP1C3T100 Device Pin Information Chapter 2. Cyclone EP1C3T144 Device Pin Information Chapter 3. Cyclone EP1C6 Device Pin Information Chapter 4. Cyclone EP1C12 Device Pin Information Chapter 5. Cyclone EP1C20 Device Pin Information Chapter 6. Package Information for Cyclone Devices Chapter 7. Designing with FineLine BGA Packages Revision History The table below shows the revision history for Chapter 7. Chapter(s) Date / Version 12 May 2003 v1.0 v1.03 Changes Made Updated Table 7-6. Updated the "PCB Layout for FineLine BGA Packages" section and Table 7-6. Minor updates. Updated Table 7-6. v1.02 v1.01 Altera Corporation Section I-1 Preliminary PCB Layout Guidelines Cyclone Device Handbook, Volume 2 Section I-2 Preliminary Altera Corporation 1. Cyclone EP1C3T100 Device Pin Information C52001-1.0 Introduction The following tables contain pin information for the Cyclone EP1C3T100 device, organized into the following sections: Section Page Pin List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 PLL & Bank Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Altera Corporation May 2003 1-1 Preliminary Pin List Table 1-1 shows the complete pin list for the Cyclone EP1C3T100 device: 1-2 Preliminary Table 1-1. Pin List for the Cyclone EP1C3T100 Device (Part 1 of 5) Device Optional Function(s) Bank Number B1 B1 CLKUSR B1 B1 B1 B1 nCSO DATA0 nCONFIG B1 B1 B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 B1 VREF1B1 VREF1B1 nCEO nCE MSEL0 MSEL1 DCLK ASDO B1 B1 B1 B1 B1 B1 B1 B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF2B1 VREF2B1 VREF1B1 VREF0B1 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VREF0B1 VREF0B1 4 B1 VREF0B1 3 VREF0B1 2 VREF0B1 1 Package Pin Name / Function VREF Bank INIT_DONE Configuration Function DQS for X8 in 100-Pin Thin Quad 100-Pin Thin Quad Flat Pack Flat Pack IO IO Cyclone Device Handbook, Volume 2 IO IO VREF0B1 VCCIO1 GND IO VREF1B1 IO DATA0 nCONFIG VCCA_PLL1 CLK0 GNDA_PLL1 nCEO nCE MSEL0 MSEL1 DCLK IO VCCIO1 Altera Corporation May 2003 GND Table 1-1. Pin List for the Cyclone EP1C3T100 Device (Part 2 of 5) Device Optional Function(s) Bank Number B1 B1 B1 B1 B1 B1 B4 B4 B4 B4 B4 B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREF2B4 VREF2B4 VREF2B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF0B4 VREF0B4 VREF2B4 VREF2B4 VREF2B4 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 DM1B DQ1B4 DQS1B DQ1B7 DQ1B6 DQ1B5 VREF2B1 25 VREF2B1 24 VREF2B1 23 VREF2B1 22 VREF2B1 21 VREF2B1 20 Package Altera Corporation May 2003 Pin Name / Function VREF Bank Configuration Function DQS for X8 in 100-Pin Thin Quad 100-Pin Thin Quad Flat Pack Flat Pack IO VREF2B1 IO IO IO IO IO IO IO IO IO GND VCCIO4 GND VCCINT IO DPCLK7 IO VREF2B4 IO IO IO VREF1B4 IO IO IO VREF0B4 1-3 Preliminary Pin List IO DPCLK6 Table 1-1. Pin List for the Cyclone EP1C3T100 Device (Part 3 of 5) Device Optional Function(s) Bank Number VREF0B4 VREF0B4 B4 B4 B4 B4 B4 B4 B3 B3 B3 B3 B3 B3 B3 B3 B3 CONF_DONE nSTATUS TCK TMS TDO B3 B3 B3 B3 B3 B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF2B3 VREF0B4 VREF0B4 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 DM0R DQ0R7 DQ0R6 DQ0R5 DQ0R4 VREF0B4 48 VREF0B4 47 VREF0B4 46 DQ1B3 DQ1B2 DQ1B1 DQ1B0 VREF0B4 45 44 43 1-4 Preliminary Package Pin Name / Function VREF Bank Configuration Function DQS for X8 in 100-Pin Thin Quad 100-Pin Thin Quad Flat Pack Flat Pack GND VCCINT GND VCCIO4 Cyclone Device Handbook, Volume 2 IO IO IO IO IO IO IO IO IO IO IO VREF2B3 GND VCCIO3 CONF_DONE nSTATUS TCK TMS TDO Altera Corporation May 2003 IO Table 1-1. Pin List for the Cyclone EP1C3T100 Device (Part 4 of 5) Device Optional Function(s) Bank Number B3 TDI B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B2 B2 B2 B2 B2 B2 VREF0B3 VREF0B3 VREF0B3 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 B2 B2 B2 VREF0B2 VREF0B2 VREF1B2 VREF0B3 73 74 75 76 77 78 79 80 81 82 83 84 85 86 DQ1T0 DQ1T1 DQ1T2 DQ1T3 DQ0R0 VREF0B3 VREF0B3 72 VREF0B3 71 VREF0B3 70 VREF0B3 69 VREF1B3 68 DQ0R3 DQ0R2 DQ0R1 DQS0R B3 VREF1B3 67 VREF1B3 66 Package Altera Corporation May 2003 Pin Name / Function VREF Bank Configuration Function DQS for X8 in 100-Pin Thin Quad 100-Pin Thin Quad Flat Pack Flat Pack CLK2 TDI IO VREF1B3 IO IO IO IO DPCLK4 GND VCCIO3 IO VREF0B3 IO IO IO IO IO IO VCCIO2 GND VCCINT GND IO DPCLK3 IO VREF0B2 1-5 Preliminary Pin List IO Table 1-1. Pin List for the Cyclone EP1C3T100 Device (Part 5 of 5) Device Optional Function(s) Bank Number B2 B2 B2 B2 B2 B2 VREF2B2 VREF2B2 B2 B2 B2 B2 DEV_OE DEV_CLRn B2 B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 93 94 95 96 97 98 99 100 DQ1T4 DQ1T5 DQ1T6 DQ1T7 VREF2B2 92 VREF2B2 91 DQS1T VREF2B2 90 VREF1B2 89 DM1T VREF1B2 88 VREF1B2 87 1-6 Preliminary Package Pin Name / Function VREF Bank Configuration Function DQS for X8 in 100-Pin Thin Quad 100-Pin Thin Quad Flat Pack Flat Pack IO IO VREF1B2 IO IO Cyclone Device Handbook, Volume 2 IO VREF2B2 IO DPCLK2 VCCINT GND VCCIO2 GND IO IO IO IO Altera Corporation May 2003 Pin Definitions Table 1-2 shows pin definitions for the EP1C3T100 device. (Part 1 of 3) Pin Description Table 1-2. Pin Definitions for the Cyclone EP1C3T100 Device Pin Type (1st, 2nd, & 3rd Function) Supply and Reference Pins Power Altera Corporation May 2003 These are I/O supply voltage pins for banks 1 through 4. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all I/O standards. VCCIO also supplies power to the input buffers used for the LVTTL, LVCMOS, 1.5-V, 1.8-V, 2.5-V, and 3.3-V PCI I/O standards. These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVDS, SSTL2, and SSTL3 I/O standards. Input reference voltage for banks 1-4. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. If voltage reference I/O standards are not used in the bank, the VREF pins are available as user I/O pins. Analog power for PLLs[1..2]. The designer must connect this pin to 1.5 V, even if the PLL is not used. Analog ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board. Power I/O, Input Power Ground Pin Name VCCIO[1..4] VCCINT VREF[0..2]B[1..4] VCCA_PLL[1..2] GNDA_PLL[1..2] Configuration and JTAG Pins Bidirectional (open-drain) Bidirectional (open-drain) Input This is a dedicated configuration status pin; it is not available as a user I/O pin. This is a dedicated configuration status pin; it is not available as a user I/O pin. Dedicated configuration control input. A low transition resets the target device; a low-to-high transition begins configuration. All I/O pins tri-state when nCONFIG is driven low. In passive serial configuration mode, DCLK is a clock input used to clock configuration data from an external source into the Cyclone device. In active serial configuration mode, DCLK is a clock output from the Cyclone device (the Cyclone device acts as master in this mode). This is a dedicated pin used for configuration. Dedicated configuration data input pin. CONF_DONE nSTATUS nCONFIG DCLK Input (PS mode), Output (AS mode) Pin Definitions 1-7 Preliminary Input DATA0 Table 1-2. Pin Definitions for the Cyclone EP1C3T100 Device Pin Type (1st, 2nd, & 3rd Function) Pin Description Active-low chip enable. Dedicated chip enable input used to detect which device is active in a chain of devices. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Output that drives low when device configuration is complete. During multi-device configuration, this pin feeds a subsequent device's nCE pin. Active serial data output from the Cyclone device. This output pin is utilized during active serial configuration mode. The Cyclone device controls configuration and drives address and control information out on ASDO. In passive serial configuration, this pin is available as a user I/O pin. Chip select output that enables/disables a serial configuration device. This output is utilized during active serial configuration mode. The Cyclone device controls configuration and enables the serial configuration device by driving nCSO low. In passive serial configuration, this pin is available as a user I/O pin. This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, the pin indicates when the device has entered user mode. This pin can be used as a user I/O pin after configuration. Optional user-supplied clock input. Synchronizes the initialization of one or more devices. This pin can be used as a user I/O pin after configuration. Dual-purpose pin that can override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as defined in the design. Dual-purpose pin that can override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design. Dedicated mode select control pins that set the configuration mode for the device. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG output pin. Input (Part 2 of 3) 1-8 Preliminary Output I/O, Output I/O, Output I/O, Output (open-drain) I/O, Input I/O, Input I/O, Input Input Input Input Input Output Pin Name nCE nCEO Cyclone Device Handbook, Volume 2 ASDO nCSO INIT_DONE CLKUSR DEV_CLRn DEV_OE MSEL[1..0] TMS TDI TCK Altera Corporation May 2003 TDO Table 1-2. Pin Definitions for the Cyclone EP1C3T100 Device Pin Type (1st, 2nd, & 3rd Function) Pin Description Clock and PLL Pins Input Input I/O Dedicated global clock input. The dual-function of CLK0 is LVDSCLK1p, which is used for differential input to PLL1. Dedicated global clock input. The dual-function of CLK2 is LVDSCLK2p, which is used for differential input to PLL2. Dual-purpose clock pins that can connect to the global clock network. These pins can be used for high fan-out control signals, such as clocks, clears, IRDY, TRDY, or DQS signals. These pins are also available as user I/O pins. (Part 3 of 3) Altera Corporation May 2003 Pin Name CLK0 CLK2 DPCLK[7..0] Dual-Purpose External Memory Interface Pins I/O Optional data strobe signal for use in external memory interfacing. These pins also function as DPCLK pins; therefore, the DQS signals can connect to the global clock network. A programmable delay chain is used to shift the DQS signals by 90 or 72 degrees. Optional data signal for use in external memory interfacing. Optional data mask output signal for use in external memory interfacing. DQS[0..1][L,R,T,B] DQ[0..7][L,R,T,B] I/O I/O DM[0..1][L,R,T,B] Pin Definitions 1-9 Preliminary Cyclone Device Handbook, Volume 2 PLL & Bank Diagram Figure 1-1 shows the PLL and Bank locations for the EP1C3T100 device. Figure 1-1. PLL and Bank Diagram (1), (2) VREF2B2 VREF1B2 VREF0B2 B2 VREF0B1 VREF0B3 VREF1B1 PLL1 VREB2B1 B4 VREF2B4 Notes for Figure 1-1: (1) (2) This is a top view of the silicon die. This is a pictoral representation only to get an idea of placement on the device. Refer to the pin-list and VREF1B4 VREF0B4 1-10 Preliminary Altera Corporation May 2003 VREB2B3 VREF1B3 B1 B3 2. Cyclone EP1C3T144 Device Pin Information C52002-1.0 Introduction The following tables contain pin information for the Cyclone EP1C3T144 device, organized into the following sections: Section Page Pin List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 PLL & Bank Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Altera Corporation May 2003 2-1 Preliminary Pin List Table 2-1 shows the complete pin list for the Cyclone EP1C3T144 device: 2-2 Preliminary Table 2-1. Pin List for the Cyclone EP1C3T144 Device (Part 1 of 7) Device Optional Function(s) Bank Number B1 B1 CLKUSR B1 B1 B1 B1 B1 B1 B1 B1 nCSO DATA0 nCONFIG B1 B1 B1 VREF0B1 VREF0B1 VREF0B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 B1 B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 nCEO nCE B1 B1 VREF1B1 VREF1B1 VREF0B1 VREF0B1 VREF0B1 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DQ1L2 DQ1L3 VREF0B1 4 B1 VREF0B1 3 VREF0B1 2 VREF0B1 1 Package Pin Name/ Function VREF Bank INIT_DONE Configuration Function DQS for X8 in 144-Pin Thin Quad 144-Pin Thin Quad Flat Pack Flat Pack DM1L DQ1L0 DQ1L1 IO LVDS4p IO LVDS4n Cyclone Device Handbook, Volume 2 IO LVDS3p IO LVDS3n IO VREF0B1 IO LVDS2p IO LVDS2n VCCIO1 GND IO DPCLK1 IO VREF1B1 IO DATA0 nCONFIG VCCA_PLL1 CLK0 LVDSCLK1p CLK1 LVDSCLK1n GNDA_PLL1 GNDG_PLL1 nCEO Altera Corporation May 2003 nCE Table 2-1. Pin List for the Cyclone EP1C3T144 Device (Part 2 of 7) Device Optional Function(s) Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B4 B4 B4 B4 B4 B4 B4 B4 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B1 VREF2B1 VREF2B1 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 DQ1B7 DQ1B6 DQ1B5 DQ1B4 DQ1L4 DQ1L5 DQ1L6 DQ1L7 VREF1B1 27 DQS1L VREF1B1 26 VREF1B1 25 VREF1B1 24 VREF1B1 23 VREF1B1 22 Package Altera Corporation May 2003 Pin Name/ Function VREF Bank MSEL0 MSEL1 DCLK ASDO Configuration Function DQS for X8 in 144-Pin Thin Quad 144-Pin Thin Quad Flat Pack Flat Pack MSEL0 MSEL1 DCLK IO IO PLL1_OUTp IO PLL1_OUTn IO DPCLK0 VCCIO1 GND IO VREF2B1 IO IO LVDS1p IO LVDS1n IO LVDS0p IO LVDS0n IO LVDS33p IO LVDS33n IO LVDS32p IO LVDS32n IO LVDS31p IO LVDS31n GND 2-3 Preliminary Pin List VCCIO4 Table 2-1. Pin List for the Cyclone EP1C3T144 Device (Part 3 of 7) Device Optional Function(s) Bank Number VREF2B4 VREF2B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 B4 B4 B4 VREF0B4 VREF0B4 VREF0B4 VREF1B4 VREF1B4 VREF2B4 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 DQ1B3 DM1B VREF2B4 50 VREF2B4 49 VREF2B4 48 VREF2B4 47 46 DQS1B 45 2-4 Preliminary Package Pin Name/ Function VREF Bank Configuration Function DQS for X8 in 144-Pin Thin Quad 144-Pin Thin Quad Flat Pack Flat Pack GND VCCINT IO DPCLK7 IO VREF2B4 Cyclone Device Handbook, Volume 2 IO IO LVDS30p IO LVDS30n IO LVDS29p IO LVDS29n IO LVDS28p IO LVDS28n IO VREF1B4 IO LVDS27p IO LVDS27n IO LVDS26p IO LVDS26n IO VREF0B4 IO DPCLK6 GND VCCINT GND VCCIO4 Altera Corporation May 2003 IO LVDS25p Table 2-1. Pin List for the Cyclone EP1C3T144 Device (Part 4 of 7) Device Optional Function(s) Bank Number B4 B4 B4 B4 B4 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 CONF_DONE nSTATUS TCK TMS TDO B3 B3 B3 B3 B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF2B3 VREF2B3 VREF2B3 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 DQS1R DQ1R5 DQ1R4 DM1R DQ1R7 DQ1R6 VREF2B3 73 VREF0B4 72 VREF0B4 71 VREF0B4 70 VREF0B4 69 VREF0B4 68 DQ1B2 DQ1B1 DQ1B0 Package Altera Corporation May 2003 Pin Name/ Function VREF Bank Configuration Function DQS for X8 in 144-Pin Thin Quad 144-Pin Thin Quad Flat Pack Flat Pack IO LVDS25n IO LVDS24p IO LVDS24n IO LVDS23p IO LVDS23n IO LVDS22n IO LVDS22p IO LVDS21n IO LVDS21p IO LVDS20n IO LVDS20p IO VREF2B3 GND VCCIO3 IO DPCLK5 IO LVDS19n IO LVDS19p IO CONF_DONE nSTATUS TCK TMS 2-5 Preliminary Pin List TDO Table 2-1. Pin List for the Cyclone EP1C3T144 Device (Part 5 of 7) Device Optional Function(s) Bank Number B3 B3 B3 B3 TDI B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B2 B2 B2 B2 B2 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B3 VREF0B3 VREF0B3 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 DQ0T0 DQ0T1 DQ0T2 DQ1R0 VREF1B3 96 DQ1R3 DQ1R2 DQ1R1 B3 VREF1B3 95 VREF1B3 94 VREF1B3 93 VREF1B3 92 VREF1B3 91 2-6 Preliminary Package Pin Name/ Function VREF Bank Configuration Function DQS for X8 in 144-Pin Thin Quad 144-Pin Thin Quad Flat Pack Flat Pack IO CLK3 LVDSCLK2n CLK2 LVDSCLK2p IO Cyclone Device Handbook, Volume 2 TDI IO VREF1B3 IO IO LVDS18n IO LVDS18p IO DPCLK4 GND VCCIO3 IO IO VREF0B3 IO LVDS17n IO LVDS17p IO LVDS16n IO LVDS16p IO LVDS15n IO LVDS15p IO LVDS14n IO LVDS14p Altera Corporation May 2003 IO LVDS13n Table 2-1. Pin List for the Cyclone EP1C3T144 Device (Part 6 of 7) Device Optional Function(s) Bank Number B2 B2 B2 VREF0B2 VREF0B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF1B2 VREF0B2 VREF0B2 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 DM0T VREF0B2 119 118 DQS0T 117 VREF0B2 116 VREF0B2 115 VREF0B2 114 DQ0T3 Package Altera Corporation May 2003 Pin Name/ Function VREF Bank Configuration Function DQS for X8 in 144-Pin Thin Quad 144-Pin Thin Quad Flat Pack Flat Pack IO LVDS13p VCCIO2 GND VCCINT GND IO DPCLK3 IO VREF0B2 IO LVDS12n IO LVDS12p IO LVDS11n IO LVDS11p IO VREF1B2 IO LVDS10n IO LVDS10p IO LVDS9n IO LVDS9p IO LVDS8n IO LVDS8p IO IO VREF2B2 IO DPCLK2 VCCINT 2-7 Preliminary Pin List GND Table 2-1. Pin List for the Cyclone EP1C3T144 Device (Part 7 of 7) Device Optional Function(s) Bank Number B2 B2 B2 B2 B2 B2 DEV_OE DEV_CLRn B2 VREF2B2 B2 VREF2B2 143 144 VREF2B2 142 VREF2B2 141 VREF2B2 140 VREF2B2 139 VREF2B2 138 DQ0T4 DQ0T5 DQ0T6 DQ0T7 VREF2B2 137 2-8 Preliminary Package Pin Name/ Function VREF Bank Configuration Function DQS for X8 in 144-Pin Thin Quad 144-Pin Thin Quad Flat Pack Flat Pack VCCIO2 GND IO LVDS7n IO LVDS7p Cyclone Device Handbook, Volume 2 IO LVDS6n IO LVDS6p IO LVDS5n IO LVDS5p Altera Corporation May 2003 Pin Definitions Table 2-2 shows pin definitions for the EP1C3T144 device. (Part 1 of 4) Pin Description Supply and Reference Pins Power These are I/O supply voltage pins for banks 1 through 4. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all I/O standards. VCCIO also supplies power to the input buffers used for the LVTTL, LVCMOS, 1.5-V, 1.8V, 2.5-V, and 3.3-V PCI I/O standards. These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVDS, SSTL2, and SSTL3 I/O standards. Input reference voltage for banks 1-4. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. If voltage reference I/O standards are not used in the bank, the VREF pins are available as user I/O pins. Analog power for PLLs[1..2]. The designer must connect this pin to 1.5 V, even if the PLL is not used. Analog ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board. Guard ring ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board. Table 2-2. Pin Definitions for the EP1C3T144 Device Pin Type (1st, 2nd, & 3rd Function) Altera Corporation May 2003 Power I/O, Input Power Ground Ground Pin Name VCCIO[1..4] VCCINT VREF[0..2]B[1..4] VCCA_PLL[1..2] GNDA_PLL[1..2] GNDG_PLL[1..2] Configuration and JTAG Pins Bidirectional (open-drain) Bidirectional (open-drain) Input Input (PS mode), Output (AS mode) This is a dedicated configuration status pin; it is not available as a user I/O pin. This is a dedicated configuration status pin; it is not available as a user I/O pin. Dedicated configuration control input. A low transition resets the target device; a low-tohigh transition begins configuration. All I/O pins tri-state when nCONFIG is driven low. CONF_DONE nSTATUS nCONFIG Pin Definitions DCLK In passive serial configuration mode, DCLK is a clock input used to clock configuration data from an external source into the Cyclone device. In active serial configuration mode, DCLK is a clock output from the Cyclone device (the Cyclone device acts as master in this mode). This is a dedicated pin used for configuration. 2-9 Preliminary Table 2-2. Pin Definitions for the EP1C3T144 Device Pin Type (1st, 2nd, & 3rd Function) Pin Description Dedicated configuration data input pin. Active-low chip enable. Dedicated chip enable input used to detect which device is active in a chain of devices. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Output that drives low when device configuration is complete. During multi-device configuration, this pin feeds a subsequent device's nCE pin. Active serial data output from the Cyclone device. This output pin is utilized during active serial configuration mode. The Cyclone device controls configuration and drives address and control information out on ASDO. In passive serial configuration, this pin is available as a user I/O pin. Chip select output that enables/disables a serial configuration device. This output is utilized during active serial configuration mode. The Cyclone device controls configuration and enables the serial configuration device by driving nCSO low. In passive serial configuration, this pin is available as a user I/O pin. This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, the pin indicates when the device has entered user mode. This pin can be used as a user I/O pin after configuration. Optional user-supplied clock input. Synchronizes the initialization of one or more devices. This pin can be used as a user I/O pin after configuration. Dual-purpose pin that can override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as defined in the design. Dual-purpose pin that can override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design. Dedicated mode select control pins that set the configuration mode for the device. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. Input Input (Part 2 of 4) 2-10 Preliminary Output I/O, Output I/O, Output I/O, Output (open-drain) I/O, Input I/O, Input I/O, Input Input Input Input Input Pin Name DATA0 nCE nCEO Cyclone Device Handbook, Volume 2 ASDO nCSO INIT_DONE CLKUSR DEV_CLRn DEV_OE MSEL[1..0] TMS TDI Altera Corporation May 2003 TCK Table 2-2. Pin Definitions for the EP1C3T144 Device Pin Type (1st, 2nd, & 3rd Function) Pin Description This is a dedicated JTAG output pin. Output (Part 3 of 4) Pin Name Altera Corporation May 2003 TDO Clock and PLL Pins Input, LVDS Input Input, LVDS Input Input, LVDS Input Input, LVDS Input I/O Dedicated global clock input. The dual-function of CLK0 is LVDSCLK1p, which is used for differential input to PLL1. Dedicated global clock input. The dual-function of CLK1 is LVDSCLK1n, which is used for differential input to PLL1. The EP1C3T100 does not support this clock pin. Dedicated global clock input. The dual-function of CLK2 is LVDSCLK2p, which is used for differential input to PLL2. Dedicated global clock input. The dual-function of CLK3 is LVDSCLK2n, which is used for differential input to PLL2. The EP1C3T100 does not support this clock pin. Dual-purpose clock pins that can connect to the global clock network. These pins can be used for high fan-out control signals, such as clocks, clears, IRDY, TRDY, or DQS signals. These pins are also available as user I/O pins. External clock output from PLL 1. This pin can be used with differential or single ended I/O standards. If clock output from PLL1 is not used, this pin is available as a user I/O pin. The EP1C3T100 does not support this output pin. Negative terminal for external clock output from PLL1. If the clock output is single ended, this pin is available as a user I/O pin. The EP1C3T100 does not support this output pin. CLK0 CLK1 CLK2 CLK3 DPCLK[7..0] PLL1_OUTp I/O, Output PLL1_OUTn I/O, Output Pin Definitions 2-11 Preliminary Table 2-2. Pin Definitions for the EP1C3T144 Device Pin Type (1st, 2nd, & 3rd Function) Pin Description Dual-Purpose LVDS & External Memory Interface Pins I/O, LVDS RX or TX Dual-purpose LVDS I/O channels 0 to 33. These channels can be used for receiving or transmitting LVDS compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. If not used for LVDS interfacing, these pins are available as user I/O pins. The EP1C3T100 does not support LVDS I/O interfacing. Dual-purpose LVDS I/O channels 0 to 33. These channels can be used for receiving or transmitting LVDS compatible signals. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for LVDS interfacing, these pins are available as user I/O pins. The EP1C3T100 does not support LVDS I/O interfacing. Dual-purpose LVDS clock input to PLL1. If differential input to PLL1 is not required, this pin is available as the CLK0 input pin. Dual-purpose LVDS clock input to PLL1. If differential input to PLL1 is not required, this pin is available as the CLK1 input pin. The EP1C3T100 does not support this clock pin. Dual-purpose LVDS clock input to PLL2. If differential input to PLL2 is not required, this pin is available as the CLK2 input pin. Dual-purpose LVDS clock input to PLL2. If differential input to PLL2 is not required, this pin is available as the CLK3 input pin. The EP1C3T100 does not support this clock pin. Optional data strobe signal for use in external memory interfacing. These pins also function as DPCLK pins; therefore, the DQS signals can connect to the global clock network. A programmable delay chain is used to shift the DQS signals by 90 or 72 degrees. Optional data signal for use in external memory interfacing. Optional data mask output signal for use in external memory interfacing. (Part 4 of 4) 2-12 Preliminary I/O, LVDS RX or TX Input, LVDS Input Input, LVDS Input Input, LVDS Input Input, LVDS Input I/O I/O I/O Pin Name LVDS[0..33]p Cyclone Device Handbook, Volume 2 LVDS[0..33]n LVDSCLK1p LVDSCLK1n LVDSCLK2p LVDSCLK2n DQS[0..1][L,R,T,B] DQ[0..7][L,R,T,B] DM[0..1][L,R,T,B] Altera Corporation May 2003 PLL & Bank Diagram PLL & Bank Diagram Figure 2-1 shows the PLL and Bank locations for the EP1C3T144 device. Figure 2-1. PLL and Bank Diagram (1), (2) VREF2B2 VREF1B2 VREF0B2 B2 VREF0B1 VREF0B3 VREF1B1 PLL1 VREB2B1 B4 VREF2B4 Notes for Figure 2-1: (1) (2) This is a top view of the silicon die. This is a pictoral representation only to get an idea of placement on the device. Refer to the pin-list and VREF1B4 VREF0B4 Altera Corporation May 2003 2-13 Preliminary VREB2B3 VREF1B3 B1 B3 Cyclone Device Handbook, Volume 2 2-14 Preliminary Altera Corporation May 2003 3. Cyclone EP1C6 Device Pin Information C52003-1.0 Introduction The following tables contain pin information for the Cyclone EP1C6 device, organized into the following sections: Section Page Pin List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 PLL & Bank Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 Altera Corporation May 2003 3-1 Preliminary Pin List Table 3-1 shows the complete pin list for the device Cyclone EP1C6 device: 3-2 Preliminary Table 3-1. Pin List for the Cyclone EP1C6 Device (Part 1 of 14) Device 144Pin TQFP 256-Pin FineLine BGA D4 C3 C2 B1 G5 F4 D3 E4 DQ1L2 DQ1L3 DQ0L0 DQ0L1 DQ0L0 DQ0L1 DQ1L1 DQ1L0 DM1L 1 2 3 4 5 6 7 8 8 9 10 11 12 13 14 15 16 17 VREF0B1 VREF0B1 B1 VREF0B1 18 19 20 10 F5 E3 D2 E2 D1 F3 G3 F2 E1 G2 DQS0L DQ0L2 DQ0L3 DQS0L DQ0L2 DQ0L3 9 7 6 5 4 3 2 1 Package 240Pin PQFP DQS for X8 DQS for X8 in 144-Pin in 240-Pin TQFP PQFP DQS for X8 in 256-Pin FineLine BGA Pin Name / Function INIT_DONE B1 CLKUSR B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 B1 VREF0B1 VREF0B1 B1 VREF0B1 Optional Configuration Bank VREF Bank Function(s) Function Number IO LVDS14p Cyclone Device Handbook, Volume 2 IO LVDS14n IO LVDS13p IO LVDS13n IO VREF0B1 IO IO LVDS12p IO LVDS12n VCCIO1 GND IO DPCLK1 IO LVDS11p IO LVDS11n IO LVDS10p IO LVDS10n IO LVDS9p IO LVDS9n IO LVDS8p IO LVDS8n Altera Corporation May 2003 IO LVDS7p Table 3-1. Pin List for the Cyclone EP1C6 Device (Part 2 of 14) Device 144Pin TQFP 256-Pin FineLine BGA F1 DM0L 21 22 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 VREF2B1 VREF2B1 VREF2B1 33 34 35 36 37 38 39 40 41 42 L3 K1 32 31 J5 H4 J4 J3 J2 K4 K3 J1 K2 30 J6 29 H1 28 G1 27 H6 26 H3 25 H2 24 G4 23 H5 DM0L Package 240Pin PQFP DQS for X8 DQS for X8 in 144-Pin in 240-Pin TQFP PQFP DQS for X8 in 256-Pin FineLine BGA Altera Corporation May 2003 B1 B1 B1 nCSO DATA0 nCONFIG VREF1B1 B1 B1 VREF1B1 VREF1B1 nCEO nCE MSEL0 MSEL1 DCLK ASDO B1 B1 B1 B1 B1 B1 VREF1B1 VREF1B1 VREF1B1 B1 VREF1B1 B1 VREF1B1 B1 VREF1B1 B1 VREF1B1 B1 VREF1B1 VREF1B1 VREF1B1 B1 VREF1B1 B1 VREF1B1 B1 VREF1B1 VREF1B1 VREF0B1 VREF0B1 Pin Name / Function Optional Configuration Bank VREF Bank Function(s) Function Number IO LVDS7n VCCIO1 IO VREF1B1 IO DATA0 nCONFIG VCCA_PLL1 CLK0 LVDSCLK1p CLK1 LVDSCLK1n GNDA_PLL1 GNDG_PLL1 nCEO nCE MSEL0 MSEL1 DCLK IO IO PLL1_OUTp IO PLL1_OUTn GND IO 3-3 Preliminary Pin List IO LVDS6p Table 3-1. Pin List for the Cyclone EP1C6 Device (Part 3 of 14) Device 144Pin TQFP 256-Pin FineLine BGA L1 L2 M1 N1 M2 N2 M3 L5 DQS1L DQ0L4 DQ0L5 DQ0L4 DQ0L5 43 44 45 46 47 48 49 28 29 30 53 54 31 32 33 34 35 36 37 VREF2B4 VREF2B4 VREF2B4 38 55 56 57 58 59 60 61 62 63 64 M4 N3 K5 L4 R1 P2 P3 N4 R2 T2 R3 P4 DQ1L4 DQ1L5 DQ1L6 DQ1L7 52 DQ0L6 DQ0L7 DQ0L6 DQ0L7 51 50 3-4 Preliminary Package 240Pin PQFP DQS for X8 DQS for X8 in 144-Pin in 240-Pin TQFP PQFP DQS for X8 in 256-Pin FineLine BGA Pin Name / Function B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B4 B4 B4 B4 VREF2B1 VREF2B1 VREF2B4 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 Optional Configuration Bank VREF Bank Function(s) Function Number IO LVDS6n IO LVDS5p IO LVDS5n Cyclone Device Handbook, Volume 2 IO LVDS4p IO LVDS4n IO LVDS3p IO LVDS3n IO DPCLK0 VCCIO1 GND IO LVDS2p IO LVDS2n IO VREF2B1 IO IO LVDS1p IO LVDS1n IO LVDS0p IO LVDS0n IO LVDS71p IO LVDS71n IO LVDS70p Altera Corporation May 2003 IO LVDS70n Table 3-1. Pin List for the Cyclone EP1C6 Device (Part 4 of 14) Device 144Pin TQFP 256-Pin FineLine BGA R4 T4 R5 P5 DQ1B4 DQ1B5 DQ1B6 DQ1B7 DQ1B6 DQ1B7 DQ1B6 DQ1B7 39 40 41 42 43 44 45 46 47 48 49 76 77 78 79 80 81 82 83 VREF2B4 VREF2B4 VREF1B4 50 51 52 84 85 86 75 N5 N6 P6 R6 M7 T6 R7 P7 N7 R8 T8 N8 DQ1B5 DQ1B4 DQ1B5 DQ1B4 74 M6 73 M5 72 DQS1B DQS1B DQS1B 71 70 69 68 67 66 65 Package 240Pin PQFP DQS for X8 DQS for X8 in 144-Pin in 240-Pin TQFP PQFP DQS for X8 in 256-Pin FineLine BGA Altera Corporation May 2003 B4 B4 B4 B4 B4 B4 VREF2B4 VREF2B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 Pin Name / Function Optional Configuration Bank VREF Bank Function(s) Function Number IO LVDS69p IO LVDS69n IO LVDS68p IO LVDS68n GND VCCIO4 GND VCCINT IO DPCLK7 IO VREF2B4 IO LVDS67p IO LVDS67n IO LVDS66p IO LVDS66n IO IO LVDS65p IO LVDS65n IO LVDS64p IO LVDS64n IO LVDS63p IO LVDS63n 3-5 Preliminary Pin List IO LVDS62p Table 3-1. Pin List for the Cyclone EP1C6 Device (Part 5 of 14) Device 144Pin TQFP 256-Pin FineLine BGA P8 M8 53 88 54 55 91 92 56 57 58 96 97 98 59 99 100 101 102 103 104 105 VREF0B4 VREF0B4 VREF0B4 60 61 62 106 107 108 N9 R10 T11 N10 P10 R11 P11 N11 N12 M9 M11 M12 P9 95 T9 94 R9 93 M10 DM1B DM1B DM1B 90 89 87 3-6 Preliminary Package 240Pin PQFP DQS for X8 DQS for X8 in 144-Pin in 240-Pin TQFP PQFP DQS for X8 in 256-Pin FineLine BGA Pin Name / Function B4 B4 VREF1B4 VREF1B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 Optional Configuration Bank VREF Bank Function(s) Function Number IO LVDS62n IO GND Cyclone Device Handbook, Volume 2 VCCINT GND VCCIO4 IO VREF1B4 IO LVDS61p IO LVDS61n IO LVDS60p IO LVDS60n IO LVDS59p IO LVDS59n IO LVDS58p IO LVDS58n IO LVDS57p IO LVDS57n IO LVDS56p IO LVDS56n IO IO VREF0B4 Altera Corporation May 2003 IO DPCLK6 Table 3-1. Pin List for the Cyclone EP1C6 Device (Part 6 of 14) Device 144Pin TQFP 256-Pin FineLine BGA 63 64 65 66 67 68 69 70 117 118 71 72 73 74 75 76 77 78 79 VREF2B3 VREF2B3 VREF2B3 80 81 121 122 123 124 125 126 127 128 129 130 120 119 T15 R15 N13 P14 P15 R16 N15 N16 K12 K14 DQ1R6 DQ1R6 DQ1R7 DQ1R6 DQ1R7 DQ1R7 P13 R14 116 R13 115 T13 114 R12 DQ1B2 DQ1B1 DQ1B0 113 P12 DQ1B3 112 DQ1B3 DQ1B2 DQ1B1 DQ1B0 DQ1B3 DQ1B2 DQ1B1 DQ1B0 111 110 109 Package 240Pin PQFP DQS for X8 DQS for X8 in 144-Pin in 240-Pin TQFP PQFP DQS for X8 in 256-Pin FineLine BGA Altera Corporation May 2003 VREF0B4 VREF0B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 Pin Name / Function Optional Configuration Bank VREF Bank Function(s) Function Number GND VCCINT GND VCCIO4 IO LVDS55p IO LVDS55n IO LVDS54p IO LVDS54n IO LVDS53p IO LVDS53n IO LVDS52p IO LVDS52n IO LVDS51n IO LVDS51p IO LVDS50n IO LVDS50p IO LVDS49n IO LVDS49p IO VREF2B3 IO GND 3-7 Preliminary Pin List VCCIO3 Table 3-1. Pin List for the Cyclone EP1C6 Device (Part 7 of 14) Device 144Pin TQFP 256-Pin FineLine BGA L12 N14 M13 M14 L13 M15 M16 L14 L15 L16 K16 DM1R DQ1R4 DQ1R5 DQ1R5 DQ1R4 DQS1R DQS1R 82 83 84 85 135 136 137 138 139 140 141 142 143 144 86 87 88 89 VREF1B3 VREF1B3 VREF1B3 B3 VREF1B3 92 90 91 145 146 147 148 149 150 151 152 K15 J16 K13 J13 J14 J15 H15 J12 J11 H16 134 133 132 131 3-8 Preliminary Package 240Pin PQFP DQS for X8 DQS for X8 in 144-Pin in 240-Pin TQFP PQFP DQS1R DQ1R5 DQ1R4 Pin Name / Function B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 CONF_DON E nSTATUS TCK TMS TDO B3 B3 B3 B3 VREF1B3 VREF1B3 VREF1B3 B3 VREF1B3 VREF1B3 VREF1B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 Optional Configuration Bank VREF Bank Function(s) Function Number DQS for X8 in 256-Pin FineLine BGA IO DPCLK5 IO LVDS48n IO LVDS48p Cyclone Device Handbook, Volume 2 IO LVDS47n IO LVDS47p IO LVDS46n IO LVDS46p IO LVDS45n IO LVDS45p IO LVDS44n IO LVDS44p GND IO PLL2_OUTn IO PLL2_OUTp CONF_DON E nSTATUS TCK TMS TDO GNDG_PLL2 GNDA_PLL2 Altera Corporation May 2003 CLK3 LVDSCLK2n Table 3-1. Pin List for the Cyclone EP1C6 Device (Part 8 of 14) Device 144Pin TQFP 256-Pin FineLine BGA G16 H11 H14 H12 93 94 95 96 157 158 159 160 161 162 163 164 165 166 97 98 99 100 101 VREF0B3 VREF0B3 VREF0B3 102 167 168 169 170 171 172 173 174 E13 D14 DQ1R2 DQ1R1 DQ1R2 DQ1R1 F13 F15 E16 E15 D16 D15 E14 F12 DQ1R3 DQ1R2 DQ1R1 DQ1R3 DQ1R3 F14 F16 G15 G13 G14 DM1R DM1R 156 155 154 153 Package 240Pin PQFP DQS for X8 DQS for X8 in 144-Pin in 240-Pin TQFP PQFP DQS for X8 in 256-Pin FineLine BGA Altera Corporation May 2003 B3 VREF1B3 TDI B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF1B3 B3 VREF1B3 VREF1B3 Pin Name / Function Optional Configuration Bank VREF Bank Function(s) Function Number CLK2 LVDSCLK2p VCCA_PLL2 TDI IO VREF1B3 VCCIO3 IO LVDS43n IO LVDS43p IO LVDS42n IO LVDS42p IO LVDS41n IO LVDS41p IO LVDS40n IO LVDS40p IO LVDS39n IO LVDS39p IO LVDS38n IO LVDS38p IO DPCLK4 GND VCCIO3 IO LVDS37n 3-9 Preliminary Pin List IO LVDS37p Table 3-1. Pin List for the Cyclone EP1C6 Device (Part 9 of 14) Device 144Pin TQFP 256-Pin FineLine BGA H13 G12 B16 C15 C14 D13 B15 A15 B14 C13 B13 A13 B12 188 189 190 117 118 119 VREF0B2 VREF0B2 VREF0B2 120 121 191 192 193 194 195 196 E12 E11 E9 D12 DQS0T DQS0T DQS0T C12 DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ1R0 DQ1R0 103 104 105 106 107 108 109 110 183 184 111 112 113 114 115 116 187 186 185 182 181 180 179 178 177 176 175 3-10 Preliminary Package 240Pin PQFP DQS for X8 DQS for X8 in 144-Pin in 240-Pin TQFP PQFP DQ1R0 Pin Name / Function B3 B3 B3 B3 B3 B3 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF0B2 VREF0B2 B2 B2 B2 B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 Optional Configuration Bank VREF Bank Function(s) Function Number DQS for X8 in 256-Pin FineLine BGA IO IO VREF0B3 IO LVDS36n Cyclone Device Handbook, Volume 2 IO LVDS36p IO LVDS35n IO LVDS35p IO LVDS34n IO LVDS34p IO LVDS33n IO LVDS33p IO LVDS32n IO LVDS32p IO LVDS31n IO LVDS31p VCCIO2 GND VCCINT GND IO DPCLK3 IO VREF0B2 IO Altera Corporation May 2003 IO LVDS30n Table 3-1. Pin List for the Cyclone EP1C6 Device (Part 10 of 14) Device 144Pin TQFP 256-Pin FineLine BGA D11 C11 B11 A11 B10 C10 D10 A9 B9 D9 C9 E10 DM0T DM0T DM0T 197 198 199 200 201 122 203 204 205 123 124 125 209 210 126 127 211 212 213 128 129 VREF2B2 VREF2B2 VREF2B2 130 131 214 215 216 217 218 E8 C8 D8 A8 B8 D7 208 207 206 202 Package 240Pin PQFP DQS for X8 DQS for X8 in 144-Pin in 240-Pin TQFP PQFP DQS for X8 in 256-Pin FineLine BGA Altera Corporation May 2003 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF1B2 VREF1B2 B2 B2 B2 B2 B2 B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF0B2 VREF0B2 VREF0B2 Pin Name / Function Optional Configuration Bank VREF Bank Function(s) Function Number IO LVDS30p IO LVDS29n IO LVDS29p IO LVDS28n IO LVDS28p IO LVDS27n IO LVDS27p IO LVDS26n IO LVDS26p IO LVDS25n IO LVDS25p IO VREF1B2 VCCIO2 GND VCCINT GND IO IO LVDS24n IO LVDS24p IO LVDS23n IO LVDS23p 3-11 Preliminary Pin List IO LVDS22n Table 3-1. Pin List for the Cyclone EP1C6 Device (Part 11 of 14) Device 144Pin TQFP 256-Pin FineLine BGA C7 B7 A6 E7 B6 C6 D6 D5 E6 E5 219 220 221 222 223 224 225 132 133 134 135 136 137 138 139 140 141 142 231 232 233 234 235 236 237 VREF2B2 VREF2B2 VREF2B2 143 144 238 239 240 C5 B5 A4 B4 C4 B3 A2 B2 DQ0T4 DQ0T5 DQ0T6 DQ0T7 DQ0T4 DQ0T5 DQ0T6 DQ0T7 DQ0T4 DQ0T5 DQ0T6 DQ0T7 230 229 228 227 226 3-12 Preliminary Package 240Pin PQFP DQS for X8 DQS for X8 in 144-Pin in 240-Pin TQFP PQFP DQS for X8 in 256-Pin FineLine BGA Pin Name / Function B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF2B2 VREF2B2 B2 B2 B2 B2 B2 B2 B2 B2 DEV_OE DEV_CLRn B2 B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 Optional Configuration Bank VREF Bank Function(s) Function Number IO LVDS22p IO LVDS21n IO LVDS21p Cyclone Device Handbook, Volume 2 IO IO LVDS20n IO LVDS20p IO LVDS19n IO LVDS19p IO VREF2B2 IO DPCLK2 VCCINT GND VCCIO2 GND IO LVDS18n IO LVDS18p IO LVDS17n IO LVDS17p IO LVDS16n IO LVDS16p IO LVDS15n Altera Corporation May 2003 IO LVDS15p Table 3-1. Pin List for the Cyclone EP1C6 Device (Part 12 of 14) Device 144Pin TQFP 256-Pin FineLine BGA A7 A10 G8 G10 H7 H9 J8 J10 K7 K9 T7 T10 C1 G6 P1 T3 L7 L10 T14 P16 K11 C16 Package 240Pin PQFP DQS for X8 DQS for X8 in 144-Pin in 240-Pin TQFP PQFP DQS for X8 in 256-Pin FineLine BGA Altera Corporation May 2003 Pin Name / Function Optional Configuration Bank VREF Bank Function(s) Function Number VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCIO1 VCCIO1 VCCIO1 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 3-13 Preliminary Pin List VCCIO3 Table 3-1. Pin List for the Cyclone EP1C6 Device (Part 13 of 14) Device 144Pin TQFP 256-Pin FineLine BGA A14 F10 F7 A3 A1 A16 A5 A12 F6 F8 F9 F11 G7 G9 G11 H8 H10 J7 J9 K6 K8 K10 3-14 Preliminary Package 240Pin PQFP DQS for X8 DQS for X8 in 144-Pin in 240-Pin TQFP PQFP DQS for X8 in 256-Pin FineLine BGA Pin Name / Function Optional Configuration Bank VREF Bank Function(s) Function Number VCCIO2 VCCIO2 VCCIO2 Cyclone Device Handbook, Volume 2 VCCIO2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Altera Corporation May 2003 GND Table 3-1. Pin List for the Cyclone EP1C6 Device (Part 14 of 14) Device 144Pin TQFP 256-Pin FineLine BGA L6 L8 L9 L11 T1 T5 T12 T16 Package 240Pin PQFP DQS for X8 DQS for X8 in 144-Pin in 240-Pin TQFP PQFP DQS for X8 in 256-Pin FineLine BGA Altera Corporation May 2003 Pin Name / Function Optional Configuration Bank VREF Bank Function(s) Function Number GND GND GND GND GND GND GND GND 3-15 Preliminary Pin List Pin Definitions Table 3-2 shows pin definitions for the EP1C6 device. 3-16 Preliminary Table 3-2. Pin Definitions for the EP1C6 Device (Part 1 of 4) Pin Type (1st, 2nd, & 3rd Function) Supply and Reference Pins Power These are I/O supply voltage pins for banks 1 through 4. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all I/O standards. VCCIO also supplies power to the input buffers used for the LVTTL, LVCMOS, 1.5-V, 1.8-V, 2.5-V, and 3.3-V PCI I/O standards. These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVDS, SSTL2, and SSTL3 I/O standards. Input reference voltage for banks 1-4. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. If voltage reference I/O standards are not used in the bank, the VREF pins are available as user I/O pins. Analog power for PLLs[1..2]. The designer must connect this pin to 1.5 V, even if the PLL is not used. Analog ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board. Guard ring ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board. Pin Name Pin Description Cyclone Device Handbook, Volume 2 VCCIO[1..4] VCCINT I/O, Input Power VREF[0..2]B[1..4] VCCA_PLL[1..2] Ground Ground Power GNDA_PLL[1..2] GNDG_PLL[1..2] Configuration and JTAG Pins Bidirectional (open-drain) Bidirectional (open-drain) Input This is a dedicated configuration status pin; it is not available as a user I/O pin. This is a dedicated configuration status pin; it is not available as a user I/O pin. Dedicated configuration control input. A low transition resets the target device; a low-to-high transition begins configuration. All I/O pins tri-state when nCONFIG is driven low. In passive serial configuration mode, DCLK is a clock input used to clock configuration data from an external source into the Cyclone device. In active serial configuration mode, DCLK is a clock output from the Cyclone device (the Cyclone device acts as master in this mode). This is a dedicated pin used for configuration. CONF_DONE nSTATUS nCONFIG Altera Corporation May 2003 DCLK Input (PS mode), Output (AS mode) Table 3-2. Pin Definitions for the EP1C6 Device (Part 2 of 4) Pin Type (1st, 2nd, & 3rd Function) Input Input Dedicated configuration data input pin. Active-low chip enable. Dedicated chip enable input used to detect which device is active in a chain of devices. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Output that drives low when device configuration is complete. During multi-device configuration, this pin feeds a subsequent device's nCE pin. Active serial data output from the Cyclone device. This output pin is utilized during active serial configuration mode. The Cyclone device controls configuration and drives address and control information out on ASDO. In passive serial configuration, this pin is available as a user I/O pin. Chip select output that enables/disables a serial configuration device. This output is utilized during active serial configuration mode. The Cyclone device controls configuration and enables the serial configuration device by driving nCSO low. In passive serial configuration, this pin is available as a user I/O pin. This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, the pin indicates when the device has entered user mode. This pin can be used as a user I/O pin after configuration. Optional user-supplied clock input. Synchronizes the initialization of one or more devices. This pin can be used as a user I/O pin after configuration. Dual-purpose pin that can override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as defined in the design. Dual-purpose pin that can override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design. Dedicated mode select control pins that set the configuration mode for the device. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG output pin. Pin Name Pin Description DATA0 Altera Corporation May 2003 Output I/O, Output I/O, Output I/O, Output (open-drain) I/O, Input I/O, Input I/O, Input Input Input Input Input Output nCE nCEO ASDO nCSO INIT_DONE CLKUSR DEV_CLRn DEV_OE MSEL[1..0] TMS TDI TCK Pin Definitions 3-17 Preliminary TDO Table 3-2. Pin Definitions for the EP1C6 Device (Part 3 of 4) Pin Type (1st, 2nd, & 3rd Function) Clock and PLL Pins Input, LVDS Input Input, LVDS Input Input, LVDS Input Input, LVDS Input I/O Dedicated global clock input. The dual-function of CLK0 is LVDSCLK1p, which is used for differential input to PLL1. Dedicated global clock input. The dual-function of CLK1 is LVDSCLK1n, which is used for differential input to PLL1. Dedicated global clock input. The dual-function of CLK2 is LVDSCLK2p, which is used for differential input to PLL2. Dedicated global clock input. The dual-function of CLK3 is LVDSCLK2n, which is used for differential input to PLL2. Dual-purpose clock pins that can connect to the global clock network. These pins can be used for high fan-out control signals, such as clocks, clears, IRDY, TRDY, or DQS signals. These pins are also available as user I/O pins. External clock output from PLL 1. This pin can be used with differential or single ended I/O standards. If clock output from PLL1 is not used, this pin is available as a user I/O pin. Negative terminal for external clock output from PLL1. If the clock output is single ended, this pin is available as a user I/O pin. External clock output from PLL 2. This pin can be used with differential or single ended I/O standards. If clock output from PLL2 is not used, this pin is available as a user I/O pin. The EP1C6T144 does not support this output pin. Negative terminal for external clock output from PLL2. If the clock output is single ended, this pin is available as a user I/O pin. The EP1C6T144 does not support this output pin. 3-18 Preliminary Pin Name Pin Description CLK0 CLK1 CLK2 Cyclone Device Handbook, Volume 2 CLK3 DPCLK[7..0] PLL1_OUTp I/O, Output PLL1_OUTn I/O, Output I/O, Output PLL2_OUTp PLL2_OUTn I/O, Output Dual-Purpose LVDS & External Memory Interface Pins I/O, LVDS RX or TX Dual-purpose LVDS I/O channels 0 to 71. These channels can be used for receiving or transmitting LVDS compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. If not used for LVDS interfacing, these pins are available as user I/O pins. Altera Corporation May 2003 LVDS[0..71]p Table 3-2. Pin Definitions for the EP1C6 Device (Part 4 of 4) Pin Type (1st, 2nd, & 3rd Function) I/O, LVDS RX or TX Pin Name Pin Description Dual-purpose LVDS I/O channels 0 to 71. These channels can be used for receiving or transmitting LVDS compatible signals. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for LVDS interfacing, these pins are available as user I/O pins. Dual-purpose LVDS clock input to PLL1. If differential input to PLL1 is not required, this pin is available as the CLK0 input pin. Dual-purpose LVDS clock input to PLL1. If differential input to PLL1 is not required, this pin is available as the CLK1 input pin. Dual-purpose LVDS clock input to PLL2. If differential input to PLL2 is not required, this pin is available as the CLK2 input pin. Dual-purpose LVDS clock input to PLL2. If differential input to PLL2 is not required, this pin is available as the CLK3 input pin. Optional data strobe signal for use in external memory interfacing. These pins also function as DPCLK pins; therefore, the DQS signals can connect to the global clock network. A programmable delay chain is used to shift the DQS signals by 90 or 72 degrees. Optional data signal for use in external memory interfacing. Optional data mask output signal for use in external memory interfacing. Altera Corporation May 2003 Input, LVDS Input Input, LVDS Input Input, LVDS Input Input, LVDS Input I/O I/O I/O LVDS[0..71]n LVDSCLK1p LVDSCLK1n LVDSCLK2p LVDSCLK2n DQS[0..1][L,R,T,B] DQ[0..7][L,R,T,B] DM[0..1][L,R,T,B] Pin Definitions 3-19 Preliminary Cyclone Device Handbook, Volume 2 PLL & Bank Diagram Figure shows the PLL and Bank locations for the EP1C6 device. Figure 3-1. PLL and Bank Diagram (1), (2) VREF2B2 VREF1B2 VREF0B2 B2 VREF0B1 VREF0B3 VREF1B1 PLL1 PLL2 VREB2B1 B4 VREF2B4 Notes for Figure: (1) (2) This is a top view of the silicon die. This is a pictoral representation only to get an idea of placement on the device. Refer to the pin-list and VREF1B4 VREF0B4 3-20 Preliminary Altera Corporation May 2003 VREB2B3 VREF1B3 B1 B3 4. Cyclone EP1C12 Device Pin Information C52004-1.0 Introduction The following tables contain pin information for the Cyclone EP1C12 device, organized into the following sections: Section Page Pin List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 PLL & Bank Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 Altera Corporation May 2003 4-1 Preliminary Pin List Table 4-1 shows the complete pin list for the device Cyclone EP1C12 device: 4-2 Preliminary Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 1 of 18) Device VREF Bank VREF0B1 1 VREF0B1 2 VREF0B1 3 VREF0B1 4 VREF0B1 5 VREF0B1 6 VREF0B1 7 VREF0B1 8 VREF0B1 9 VREF0B1 10 VREF0B1 11 VREF0B1 12 VREF0B1 13 VREF0B1 14 VREF0B1 15 VREF0B1 16 VREF0B1 17 VREF0B1 18 VREF0B1 19 B1 VREF0B1 20 E3 D2 E2 D1 F3 G3 F2 E1 G2 F5 F1 E4 E5 F2 F3 F4 F5 G1 G2 F6 DQS0L DQS0L DQ0L2 DQ0L3 DQ0L2 DQ0L3 DQS0L DQ0L2 DQ0L3 E4 E2 D3 E3 F4 D1 DQ0L0 DQ0L1 DQ0L0 DQ0L1 DQ0L0 DQ0L1 G5 D4 B1 D2 C2 D3 C3 C2 D4 C3 Package Pin Name / Function INIT_DONE B1 CLKUSR B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP IO LVDS23p Cyclone Device Handbook, Volume 2 IO LVDS23n IO LVDS22p IO LVDS22n IO VREF0B1 IO IO LVDS21p IO LVDS21n VCCIO1 GND IO DPCLK1 IO LVDS20p IO LVDS20n IO LVDS19p IO LVDS19n IO LVDS18p IO LVDS18n IO LVDS17p IO LVDS17n Altera Corporation May 2003 IO LVDS16p Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 2 of 18) Device VREF Bank VREF0B1 21 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 22 VREF0B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 23 VREF1B1 24 VREF1B1 25 VREF1B1 26 VREF1B1 27 B1 B1 VREF1B1 28 VREF1B1 29 VREF1B1 30 VREF1B1 31 nCEO B1 VREF1B1 32 G4 H2 H3 H6 G1 H1 J6 J5 H4 H5 H3 H4 H5 H6 J1 H7 J2 J5 J3 J4 K1 J6 K2 DM0L H2 H1 G6 G5 G4 G3 DQ0L4 DQ0L5 DQ0L6 DQ0L7 F1 F7 DM0L DM0L Package Altera Corporation May 2003 Pin Name / Function B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 nCSO DATA0 nCONFIG B1 B1 B1 Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP IO LVDS16n IO LVDS15p IO LVDS15n IO LVDS14p IO LVDS14n IO VCCIO1 GND IO LVDS13p IO LVDS13n IO LVDS12p IO LVDS12n IO VREF1B1 IO DATA0 nCONFIG VCCA_PLL1 CLK0 LVDSCLK1p CLK1 LVDSCLK1n GNDA_PLL1 GNDG_PLL1 4-3 Preliminary Pin List nCEO Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 3 of 18) Device VREF Bank VREF1B1 33 VREF1B1 34 VREF1B1 35 VREF1B1 36 VREF1B1 37 VREF1B1 38 VREF1B1 39 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF2B1 VREF2B1 40 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 41 VREF2B1 42 B1 VREF2B1 43 L3 K1 L1 M1 M3 M2 M5 M4 N1 N2 DQ1L0 DQ1L1 DQ1L2 DQ1L3 L2 L3 L5 L4 L6 L7 K2 K5 DM1L J1 K4 K3 K6 K4 L1 J2 K7 J3 K3 J4 J7 4-4 Preliminary Package Pin Name / Function nCE MSEL0 MSEL1 DCLK ASDO B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP nCE MSEL0 MSEL1 Cyclone Device Handbook, Volume 2 DCLK IO IO PLL1_OUTp IO PLL1_OUTn IO LVDS11p IO LVDS11n IO LVDS10p IO LVDS10n IO LVDS9p IO LVDS9n VCCIO1 GND IO IO LVDS8p IO LVDS8n IO LVDS7p IO LVDS7n IO LVDS6p Altera Corporation May 2003 IO LVDS6n Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 4 of 18) Device VREF Bank VREF2B1 44 VREF2B1 45 VREF2B1 46 VREF2B1 47 VREF2B1 48 VREF2B1 49 VREF2B1 50 VREF2B1 51 VREF2B1 52 VREF2B1 53 VREF2B1 54 VREF2B1 55 VREF2B1 56 VREF2B1 57 VREF2B1 58 VREF2B1 59 VREF2B1 60 VREF2B4 61 VREF2B4 62 VREF2B4 63 VREF2B4 64 B4 VREF2B4 65 R1 P2 P3 N4 R2 T2 R3 P4 R4 L4 K5 N3 M4 P2 P3 R1 P4 R2 R3 T2 T3 U3 V4 M8 N8 T4 DQ0L6 DQ0L7 DQ0L6 DQ0L7 DQ1L6 DQ1L7 L5 P5 M3 N4 N2 N3 DQ0L4 DQ0L5 M2 N6 DQ0L4 DQ0L5 DQ1L4 DQ1L5 DQS1L N1 N5 M1 N7 L2 M6 Package Altera Corporation May 2003 Pin Name / Function B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B4 B4 B4 B4 Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP IO LVDS5p IO LVDS5n IO LVDS4p IO LVDS4n IO LVDS3p IO LVDS3n IO DPCLK0 VCCIO1 GND IO LVDS2p IO LVDS2n IO VREF2B1 IO IO LVDS1p IO LVDS1n IO LVDS0p IO LVDS0n IO LVDS102p IO LVDS102n IO LVDS101p IO LVDS101n 4-5 Preliminary Pin List IO LVDS100p Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 5 of 18) Device VREF Bank VREF2B4 66 VREF2B4 67 VREF2B4 68 VREF2B4 69 VREF2B4 70 VREF2B4 71 VREF2B4 72 B4 B4 B4 B4 B4 B4 B4 B4 VREF2B4 80 VREF2B4 81 B4 B4 B4 B4 B4 VREF2B4 82 VREF2B4 83 VREF2B4 84 VREF2B4 85 VREF1B4 86 T6 R7 P7 N7 R8 U7 V7 T7 R7 U8 DQ1B3 DQ1B2 DQ1B1 DQ1B0 VREF2B4 VREF2B4 79 M7 VREF2B4 78 R6 VREF2B4 77 P6 VREF2B4 76 N6 VREF2B4 75 N5 V6 U6 P6 P7 T6 R6 DQ1B5 DQ1B5 DQ1B4 DQ1B4 DQ1B5 DQ1B4 VREF2B4 74 M6 R5 VREF2B4 73 M5 R4 DQS1B DQS1B DQS1B P5 U5 R5 T5 DQ1B7 DQ1B7 DQ1B6 DQ1B6 T4 U4 DQ1B7 DQ1B6 4-6 Preliminary Package Pin Name / Function B4 B4 B4 B4 B4 Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP IO LVDS100n IO LVDS99p IO LVDS99n Cyclone Device Handbook, Volume 2 GND VCCIO4 GND VCCINT IO DPCLK7 IO VREF2B4 IO LVDS98p IO LVDS98n IO LVDS97p IO LVDS97n IO LVDS96p IO LVDS96n GND VCCINT IO LVDS95p IO LVDS95n IO LVDS94p IO LVDS94n Altera Corporation May 2003 IO LVDS93p Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 6 of 18) Device VREF Bank VREF1B4 87 VREF1B4 88 VREF1B4 VREF1B4 89 VREF1B4 90 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREF1B4 VREF1B4 94 VREF1B4 95 VREF1B4 96 VREF1B4 97 B4 B4 VREF1B4 VREF1B4 98 P9 P10 R11 R9 T9 VREF1B4 VREF1B4 93 VREF1B4 M10 VREF1B4 VREF1B4 P8 VREF1B4 N8 R9 T9 M9 N9 P9 U10 V10 T10 R10 DM1B DM1B VREF1B4 V9 DM1B VREF1B4 U9 VREF1B4 92 VREF1B4 91 R8 M8 T8 T8 V8 Package Altera Corporation May 2003 Pin Name / Function B4 B4 B4 Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP IO LVDS93n IO LVDS92p IO LVDS92n GND VCCINT GND VCCIO4 IO LVDS91p IO LVDS91n IO LVDS90p IO LVDS90n IO LVDS89p IO LVDS89n IO VREF1B4 IO LVDS88p IO LVDS88n IO LVDS87p IO LVDS87n GND VCCINT IO 4-7 Preliminary Pin List IO LVDS86p Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 7 of 18) Device VREF Bank VREF1B4 99 VREF1B4 100 VREF1B4 101 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF0B4 102 VREF0B4 103 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREF0B4 104 VREF0B4 105 VREF0B4 106 VREF0B4 107 VREF0B4 108 VREF0B4 109 VREF0B4 110 VREF0B4 N11 N12 M9 M11 M12 VREF0B4 VREF0B4 VREF0B4 VREF0B4 P11 VREF0B4 R11 T12 R12 V13 U13 T13 R13 N10 M10 P12 P13 U14 DQS0B DQ0B7 DQ0B6 DQ0B5 DQ0B4 P10 U12 N10 V12 T11 V11 R10 U11 N9 T11 DM0B 4-8 Preliminary Package Pin Name / Function B4 B4 B4 B4 B4 B4 B4 Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP IO LVDS86n IO LVDS85p IO LVDS85n Cyclone Device Handbook, Volume 2 GND VCCIO4 IO LVDS84p IO LVDS84n GND VCCINT IO LVDS83p IO LVDS83n IO LVDS82p IO LVDS82n IO LVDS81p IO LVDS81n IO LVDS80p IO LVDS80n IO IO VREF0B4 IO DPCLK6 GND Altera Corporation May 2003 VCCINT Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 8 of 18) Device VREF Bank VREF0B4 111 VREF0B4 112 VREF0B4 113 VREF0B4 114 VREF0B4 115 VREF0B4 116 VREF0B4 117 VREF0B4 118 VREF0B4 119 VREF0B4 120 VREF2B3 121 VREF2B3 122 VREF2B3 123 VREF2B3 124 VREF2B3 125 VREF2B3 126 VREF2B3 127 VREF2B3 128 VREF2B3 129 VREF2B3 130 VREF2B3 131 B3 VREF2B3 132 L12 N14 P15 P14 DQS1R DQS1R DQ1R5 DQ1R5 DQS1R DQ1R5 P15 R16 N15 N16 K12 K14 P14 N13 R15 T15 U16 T15 T16 T17 R17 R18 R15 R16 P16 P17 DQ1R6 DQ1R6 DQ1R6 DQ1R7 DQ1R7 DQ1R7 P13 M11 R14 N11 R13 U15 T13 V15 R12 R14 P12 T14 DQ1B3 DQ1B3 DQ1B2 DQ1B2 DQ1B1 DQ1B1 DQ1B0 DQ1B0 DQ0B3 DQ0B2 DQ0B1 DQ0B0 Package Altera Corporation May 2003 Pin Name / Function B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP GND VCCIO4 IO LVDS79p IO LVDS79n IO LVDS78p IO LVDS78n IO LVDS77p IO LVDS77n IO LVDS76p IO LVDS76n IO LVDS75n IO LVDS75p IO LVDS74n IO LVDS74p IO LVDS73n IO LVDS73p IO VREF2B3 IO GND VCCIO3 IO DPCLK5 4-9 Preliminary Pin List IO LVDS72n Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 9 of 18) Device VREF Bank VREF2B3 133 VREF2B3 134 VREF2B3 135 VREF2B3 136 VREF2B3 137 VREF2B3 138 VREF2B3 139 VREF2B3 140 VREF2B3 141 VREF2B3 VREF2B3 VREF2B3 VREF2B3 142 VREF2B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 B3 VREF1B3 143 K15 L18 L17 M13 L13 L16 L15 L14 K16 DM1R K16 M17 M14 M15 M16 L16 M18 DQ1R3 DQ1R2 DQ1R1 DQ1R0 L15 N15 L14 N16 M16 N12 M15 N13 L13 N17 M14 N18 M13 N14 DQ1R4 DQ1R4 4-10 Preliminary Package Pin Name / Function B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP DQ1R4 IO LVDS72p IO LVDS71n IO LVDS71p Cyclone Device Handbook, Volume 2 IO LVDS70n IO LVDS70p IO LVDS69n IO LVDS69p IO LVDS68n IO LVDS68p IO LVDS67n IO LVDS67p IO GND VCCIO3 IO LVDS66n IO LVDS66p IO LVDS65n IO LVDS65p IO LVDS64n IO LVDS64p IO Altera Corporation May 2003 IO PLL2_OUTn Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 10 of 18) Device VREF Bank VREF1B3 144 VREF1B3 145 VREF1B3 146 VREF1B3 147 VREF1B3 148 VREF1B3 149 VREF1B3 150 VREF1B3 151 B3 B3 VREF1B3 154 TDI B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREF1B3 VREF1B3 VREF1B3 VREF0B3 VREF0B3 157 VREF0B3 H18 DQ0R7 VREF1B3 VREF1B3 VREF1B3 VREF1B3 156 H12 B3 VREF1B3 155 H14 H11 VREF1B3 153 G16 J15 J12 J17 J14 J13 H13 H14 H15 H16 H17 DM0R VREF1B3 152 H16 J16 J11 K12 J12 J18 H15 K13 J15 K14 J14 K18 J13 L12 K13 K17 J16 K15 Package Altera Corporation May 2003 Pin Name / Function B3 CONF_DONE B3 nSTATUS TCK TMS TDO B3 B3 B3 B3 Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP IO PLL2_OUTp CONF_DONE nSTATUS TCK TMS TDO GNDG_PLL2 GNDA_PLL2 CLK3 LVDSCLK2n CLK2 LVDSCLK2p VCCA_PLL2 TDI IO VREF1B3 IO LVDS63n IO LVDS63p IO LVDS62n IO LVDS62p IO LVDS61n IO LVDS61p GND VCCIO3 4-11 Preliminary Pin List IO Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 11 of 18) Device VREF Bank VREF0B3 VREF0B3 VREF0B3 158 VREF0B3 159 VREF0B3 160 VREF0B3 161 VREF0B3 162 VREF0B3 163 VREF0B3 164 VREF0B3 165 VREF0B3 166 VREF0B3 167 VREF0B3 168 VREF0B3 169 VREF0B3 170 VREF0B3 171 VREF0B3 172 VREF0B3 173 VREF0B3 174 VREF0B3 175 VREF0B3 176 B3 VREF0B3 177 E13 D14 H13 G12 B16 E16 E15 D18 E14 D16 DQ1R2 DQ1R2 DQ1R1 DQ1R1 DQ1R0 DQ1R0 DQ0R2 DQ0R1 DQ0R0 D15 E14 F12 D16 E15 E16 F15 F18 F17 F13 F14 F16 F15 E17 DQ1R3 DQ1R3 DQ0R3 DQS0R F13 F12 F14 G12 F16 G16 G15 G15 G13 G14 G14 G13 DM1R G17 DM1R G18 4-12 Preliminary Package Pin Name / Function B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP DQ0R6 DQ0R5 DQ0R4 IO LVDS60n IO LVDS60p IO LVDS59n Cyclone Device Handbook, Volume 2 IO LVDS59p IO LVDS58n IO LVDS58p IO LVDS57n IO LVDS57p IO LVDS56n IO LVDS56p IO LVDS55n IO LVDS55p IO LVDS54n IO LVDS54p IO DPCLK4 GND VCCIO3 IO LVDS53n IO LVDS53p IO IO VREF0B3 Altera Corporation May 2003 IO LVDS52n Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 12 of 18) Device VREF Bank VREF0B3 178 VREF0B3 179 VREF0B3 180 VREF0B2 181 VREF0B2 182 VREF0B2 183 VREF0B2 184 VREF0B2 185 VREF0B2 186 VREF0B2 187 VREF0B2 188 VREF0B2 189 VREF0B2 190 VREF0B2 191 VREF0B2 192 B2 B2 B2 B2 B2 B2 B2 VREF0B2 193 VREF0B2 194 VREF0B2 195 VREF0B2 196 VREF0B2 197 VREF0B2 VREF0B2 E12 E11 E9 D12 D11 B14 C14 E13 G10 F10 B13 A13 DQS0T DQS0T DQS0T C12 B12 A13 A15 C15 D14 B13 B15 C13 F11 DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ0T0 DQ0T1 DQ0T2 DQ0T3 B14 G11 A15 B16 B15 C16 D13 D17 C14 C17 C15 D15 Package Altera Corporation May 2003 Pin Name / Function B3 B3 B3 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP IO LVDS52p IO LVDS51n IO LVDS51p IO LVDS50n IO LVDS50p IO LVDS49n IO LVDS49p IO LVDS48n IO LVDS48p IO LVDS47n IO LVDS47p VCCIO2 GND VCCINT GND IO DPCLK3 IO VREF0B2 IO IO LVDS46n IO LVDS46p IO LVDS45n 4-13 Preliminary Pin List IO LVDS45p Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 13 of 18) Device VREF Bank VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 198 VREF0B2 199 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF1B2 204 VREF1B2 205 B2 B2 B2 B2 B2 VREF1B2 206 VREF1B2 207 VREF1B2 VREF1B2 VREF1B2 208 E10 D9 C9 C10 D10 B10 A10 E10 DM0T DM0T VREF1B2 VREF1B2 203 B9 VREF1B2 202 A9 VREF1B2 201 D10 VREF1B2 200 C10 VREF1B2 C11 D11 B11 A11 E11 DM0T VREF1B2 VREF1B2 B10 A12 VREF1B2 A11 B12 B11 C12 C11 D12 C13 D13 4-14 Preliminary Package Pin Name / Function B2 B2 B2 B2 Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP DQ0T4 DQ0T5 DQ0T6 DQ0T7 IO LVDS44n IO LVDS44p IO LVDS43n Cyclone Device Handbook, Volume 2 IO LVDS43p VCCINT GND IO LVDS42n IO LVDS42p VCCIO2 GND IO LVDS41n IO LVDS41p IO LVDS40n IO LVDS40p IO VCCINT GND IO LVDS39n IO LVDS39p IO LVDS38n IO LVDS38p Altera Corporation May 2003 IO VREF1B2 Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 14 of 18) Device VREF Bank VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 209 VREF1B2 210 VREF1B2 211 VREF1B2 212 B2 B2 B2 B2 B2 B2 B2 B2 VREF2B2 217 VREF2B2 218 VREF2B2 219 VREF2B2 220 VREF2B2 221 B2 B2 VREF2B2 VREF2B2 222 E7 D7 C7 VREF2B2 216 VREF1B2 215 B8 D7 C7 B7 A6 VREF1B2 214 A8 VREF1B2 213 E8 VREF1B2 D8 C8 A8 B8 E8 E7 A7 B7 DQ1T0 DQ1T1 DQ1T2 DQ1T3 B9 A9 D8 C9 C8 D9 F9 DM1T G9 Package Altera Corporation May 2003 Pin Name / Function B2 B2 B2 B2 B2 B2 B2 B2 Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP IO LVDS37n IO LVDS37p IO LVDS36n IO LVDS36p IO LVDS35n IO LVDS35p VCCIO2 GND VCCINT GND IO LVDS34n IO LVDS34p IO LVDS33n IO LVDS33p IO LVDS32n IO LVDS32p IO LVDS31n IO LVDS31p VCCINT GND IO LVDS30n 4-15 Preliminary Pin List IO LVDS30p Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 15 of 18) Device VREF Bank VREF2B2 223 VREF2B2 224 VREF2B2 225 VREF2B2 226 VREF2B2 227 VREF2B2 228 VREF2B2 229 VREF2B2 230 B2 B2 B2 B2 B2 B2 B2 B2 DEV_OE DEV_CLRn B2 B2 VREF2B2 238 VREF2B2 239 VREF2B2 240 VREF2B2 237 VREF2B2 236 B4 C4 B3 A2 B2 A7 A10 G8 G10 VREF2B2 235 A4 VREF2B2 234 B5 VREF2B2 233 C5 VREF2B2 232 C5 D5 A4 B4 F8 G8 B3 C4 A17 A2 B1 B18 DQ0T4 DQ0T5 DQ0T6 DQ0T7 DQ0T4 DQ0T5 DQ0T6 DQ0T7 DQ1T4 DQ1T5 DQ1T6 DQ1T7 VREF2B2 231 E5 B5 E6 A6 DQS1T D5 C6 D6 B6 C6 D6 B6 E6 4-16 Preliminary Package Pin Name / Function B2 B2 B2 B2 B2 B2 Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP IO LVDS29n IO LVDS29p IO LVDS28n Cyclone Device Handbook, Volume 2 IO LVDS28p IO VREF2B2 IO DPCLK2 VCCINT GND VCCIO2 GND IO LVDS27n IO LVDS27p IO LVDS26n IO LVDS26p IO LVDS25n IO LVDS25p IO LVDS24n IO LVDS24p VCCINT VCCINT VCCINT Altera Corporation May 2003 VCCINT Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 16 of 18) Device VREF Bank H7 H9 J8 J10 K7 K9 T7 T10 C1 G6 P1 E1 G7 M7 P1 T3 L7 L10 T14 P11 P8 V14 V5 P16 K11 C16 E18 H12 M12 V2 V17 U18 U1 L9 K10 J9 H10 Package Altera Corporation May 2003 Pin Name / Function Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 4-17 Preliminary Pin List VCCIO3 Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 17 of 18) Device VREF Bank P18 A14 F10 F7 A3 E9 A1 A16 A5 A12 F6 F8 F9 F11 G7 G9 G11 H8 H10 J7 J9 K6 A3 B17 B2 C1 C18 H11 H8 H9 J10 J11 J8 K11 K8 A18 A16 A1 E12 A5 A14 4-18 Preliminary Package Pin Name / Function Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP VCCIO3 VCCIO2 VCCIO2 Cyclone Device Handbook, Volume 2 VCCIO2 VCCIO2 VCCIO2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Altera Corporation May 2003 GND Table 4-1. Pin List for the Cyclone EP1C12 Device (Part 18 of 18) Device VREF Bank K8 K10 L6 L8 L9 L11 T1 T5 T12 T16 V1 V16 V18 V3 U2 U17 T18 T1 L8 L11 L10 K9 Package Altera Corporation May 2003 Pin Name / Function Optional Configuration Bank Function(s) Function Num. DQS for X8 in DQS for X8 in DQS for X8 in 240240256-Pin 324-Pin 256-Pin 324-Pin Pin Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA PQFP PQFP GND GND GND GND GND GND GND GND GND GND GND GND 4-19 Preliminary Pin List Pin Definitions Table 4-2 shows pin definitions for the EP1C12 device. 4-20 Preliminary Table 4-2. Pin Definitions for the EP1C12 Device (Part 1 of 4) Pin Description Supply and Reference Pins These are I/O supply voltage pins for banks 1 through 4. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all I/O standards. VCCIO also supplies power to the input buffers used for the LVTTL, LVCMOS, 1.5-V, 1.8-V, 2.5-V, and 3.3-V PCI I/O standards. These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVDS, SSTL2, and SSTL3 I/O standards. Input reference voltage for banks 1-4. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. If voltage reference I/O standards are not used in the bank, the VREF pins are available as user I/O pins. Analog power for PLLs[1..2]. The designer must connect this pin to 1.5 V, even if the PLL is not used. Analog ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board. Guard ring ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board. Pin Name Pin Type (1st, 2nd, & 3rd Function) Cyclone Device Handbook, Volume 2 VCCIO[1..4] Power VCCINT Power VREF[0..2]B[1..4] I/O, Inputz VCCA_PLL[1..2] Power GNDA_PLL[1..2] Ground GNDG_PLL[1..2] Ground Configuration and JTAG Pins This is a dedicated configuration status pin; it is not available as a user I/O pin. This is a dedicated configuration status pin; it is not available as a user I/O pin. Dedicated configuration control input. A low transition resets the target device; a low-to-high transition begins configuration. All I/O pins tri-state when nCONFIG is driven low. In passive serial configuration mode, DCLK is a clock input used to clock configuration data from an external source into the Cyclone device. In active serial configuration mode, DCLK is a clock output from the Cyclone device (the Cyclone device acts as master in this mode). This is a dedicated pin used for configuration. Dedicated configuration data input pin. CONF_DONE Bidirectional (opendrain) nSTATUS Bidirectional (opendrain) nCONFIG Input DCLK Input (PS mode), Output (AS mode) Altera Corporation May 2003 DATA0 Input Table 4-2. Pin Definitions for the EP1C12 Device (Part 2 of 4) Pin Description Active-low chip enable. Dedicated chip enable input used to detect which device is active in a chain of devices. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Output that drives low when device configuration is complete. During multi-device configuration, this pin feeds a subsequent device's nCE pin. Active serial data output from the Cyclone device. This output pin is utilized during active serial configuration mode. The Cyclone device controls configuration and drives address and control information out on ASDO. In passive serial configuration, this pin is available as a user I/O pin. Chip select output that enables/disables a serial configuration device. This output is utilized during active serial configuration mode. The Cyclone device controls configuration and enables the serial configuration device by driving nCSO low. In passive serial configuration, this pin is available as a user I/O pin. This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, the pin indicates when the device has entered user mode. This pin can be used as a user I/O pin after configuration. Optional user-supplied clock input. Synchronizes the initialization of one or more devices. This pin can be used as a user I/O pin after configuration. Dual-purpose pin that can override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as defined in the design. Dual-purpose pin that can override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design. Dedicated mode select control pins that set the configuration mode for the device. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG output pin. Pin Name Pin Type (1st, 2nd, & 3rd Function) Altera Corporation May 2003 nCE Input nCEO Output ASDO I/O, Output nCSO I/O, Output INIT_DONE I/O, Output (opendrain) CLKUSR I/O, Input DEV_CLRn I/O, Input DEV_OE I/O, Input MSEL[1..0] Input TMS Input TDI Input TCK Input TDO Output Clock and PLL Pins Dedicated global clock input. The dual-function of CLK0 is LVDSCLK1p, which is used for differential input to PLL1. Pin Definitions 4-21 Preliminary CLK0 Input, LVDS Input Table 4-2. Pin Definitions for the EP1C12 Device (Part 3 of 4) Pin Description Dedicated global clock input. The dual-function of CLK1 is LVDSCLK1n, which is used for differential input to PLL1. Dedicated global clock input. The dual-function of CLK2 is LVDSCLK2p, which is used for differential input to PLL2. Dedicated global clock input. The dual-function of CLK3 is LVDSCLK2n, which is used for differential input to PLL2. Dual-purpose clock pins that can connect to the global clock network. These pins can be used for high fan-out control signals, such as clocks, clears, IRDY, TRDY, or DQS signals. These pins are also available as user I/O pins. External clock output from PLL 1. This pin can be used with differential or single ended I/O standards. If clock output from PLL1 is not used, this pin is available as a user I/O pin. Negative terminal for external clock output from PLL1. If the clock output is single ended, this pin is available as a user I/O pin. External clock output from PLL 2. This pin can be used with differential or single ended I/O standards. If clock output from PLL2 is not used, this pin is available as a user I/O pin. Negative terminal for external clock output from PLL2. If the clock output is single ended, this pin is available as a user I/O pin. 4-22 Preliminary Pin Name Pin Type (1st, 2nd, & 3rd Function) CLK1 Input, LVDS Input CLK2 Input, LVDS Input CLK3 Input, LVDS Input Cyclone Device Handbook, Volume 2 DPCLK[7..0] I/O PLL1_OUTp I/O, Output PLL1_OUTn I/O, Output PLL2_OUTp I/O, Output PLL2_OUTn I/O, Output Dual-Purpose LVDS & External Memory Interface Pins Dual-purpose LVDS I/O channels 0 to 102. These channels can be used for receiving or transmitting LVDS compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. If not used for LVDS interfacing, these pins are available as user I/O pins. Dual-purpose LVDS I/O channels 0 to 102. These channels can be used for receiving or transmitting LVDS compatible signals. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for LVDS interfacing, these pins are available as user I/O pins. Dual-purpose LVDS clock input to PLL1. If differential input to PLL1 is not required, this pin is available as the CLK0 input pin. Dual-purpose LVDS clock input to PLL1. If differential input to PLL1 is not required, this pin is available as the CLK1 input pin. LVDS[0..102]p I/O, LVDS RX or TX LVDS[0..102]n I/O, LVDS RX or TX LVDSCLK1p Input, LVDS Input Altera Corporation May 2003 LVDSCLK1n Input, LVDS Input Table 4-2. Pin Definitions for the EP1C12 Device (Part 4 of 4) Pin Description Dual-purpose LVDS clock input to PLL2. If differential input to PLL2 is not required, this pin is available as the CLK2 input pin. Dual-purpose LVDS clock input to PLL2. If differential input to PLL2 is not required, this pin is available as the CLK3 input pin. Optional data strobe signal for use in external memory interfacing. These pins also function as DPCLK pins; therefore, the DQS signals can connect to the global clock network. A programmable delay chain is used to shift the DQS signals by 90 or 72 degrees. Optional data signal for use in external memory interfacing. Optional data mask output signal for use in external memory interfacing. Pin Name Pin Type (1st, 2nd, & 3rd Function) Altera Corporation May 2003 LVDSCLK2p Input, LVDS Input LVDSCLK2n Input, LVDS Input DQS[0..1][L,R,T,B] I/O DQ[0..7][L,R,T,B] I/O DM[0..1][L,R,T,B] I/O Pin Definitions 4-23 Preliminary Cyclone Device Handbook, Volume 2 PLL & Bank Diagram Figure 4-1 shows the PLL and bank locations for the EP1C12 device. Figure 4-1. PLL and Bank Diagram (1), (2) VREF2B2 VREF1B2 VREF0B2 B2 VREF0B1 VREF0B3 VREF1B1 PLL1 PLL2 VREB2B1 B4 VREF2B4 Notes for Figure 4-1: (1) (2) This is a top view of the silicon die. This is a pictoral representation only to get an idea of placement on the device. Refer to the pin-list and the Quartus II software for exact locations. VREF1B4 VREF0B4 4-24 Preliminary Altera Corporation May 2003 VREB2B3 VREF1B3 B1 B3 5. Cyclone EP1C20 Device Pin Information C52005-1.0 Introduction The following tables contain pin information for the Cyclone EP1C20 device, organized into the following sections: Section Page Pin List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 PLL & Bank Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 Altera Corporation May 2003 5-1 Preliminary Pin List Table 5-1 shows the complete pin list for the device Cyclone EP1C20 device: 5-2 Preliminary Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 1 of 20) Device Configuration Function VREF Bank VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 B1 B1 B1 VREF0B1 VREF0B1 VREF0B1 F1 E4 E5 F2 F3 F4 F5 G1 G2 F6 F7 F3 E3 E2 F4 F5 F2 F1 F6 G5 G1 G2 DQS0L DQ0L2 DQ0L3 DQS0L DQ0L2 DQ0L3 E2 E3 E4 E5 D1 D1 DQ0L0 DQ0L1 DQ0L0 DQ0L1 D4 D4 D2 D2 D3 D3 C2 C2 C3 C3 INIT_DONE B1 CLKUSR B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 Package Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA IO LVDS31p IO LVDS31n Cyclone Device Handbook, Volume 2 IO LVDS30p IO LVDS30n IO VREF0B1 IO IO LVDS29p IO LVDS29n VCCIO1 GND IO DPCLK1 IO LVDS28p IO LVDS28n IO LVDS27p IO LVDS27n IO LVDS26p IO LVDS26n IO LVDS25p IO LVDS25n IO LVDS24p Altera Corporation May 2003 IO LVDS24n Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 2 of 20) Device Configuration Function VREF Bank VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 B1 nCSO B1 VREF1B1 VREF1B1 J1 K2 H6 H5 H4 H3 H2 H3 H4 J1 J2 H5 H6 J3 J4 J5 J6 J7 J8 DM0L DM0L H2 H1 H1 H7 G6 G4 DQ0L6 DQ0L7 G5 G3 DQ0L5 G4 G7 DQ0L4 G3 G6 DQ0L4 DQ0L5 DQ0L6 DQ0L7 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 Package Altera Corporation May 2003 Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA IO LVDS23p IO LVDS23n IO LVDS22p IO LVDS22n IO VCCIO1 GND IO LVDS21p IO LVDS21n IO LVDS20p IO LVDS20n IO LVDS19p IO LVDS19n IO LVDS18p IO LVDS18n IO LVDS17p IO LVDS17n IO LVDS16p IO LVDS16n IO IO VREF1B1 VCCIO1 5-3 Preliminary Pin List IO Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 3 of 20) Device Configuration Function VREF Bank VREF1B1 VREF1B1 VREF1B1 B1 B1 VREF1B1 VREF1B1 nCEO nCE MSEL0 MSEL1 DCLK ASDO B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 L7 VREF1B1 K4 K5 L8 M8 M2 M1 M5 M6 M4 M3 M7 DM1L DM1L B1 VREF1B1 K6 B1 VREF1B1 L1 B1 VREF1B1 K7 B1 VREF1B1 K3 B1 VREF1B1 J7 L5 L1 L6 L3 L4 B1 VREF1B1 K2 L2 J6 L7 K1 K7 VREF1B1 J4 K6 VREF1B1 J3 K5 J5 K4 J2 K1 H7 K3 DATA0 nCONFIG B1 B1 5-4 Preliminary Package Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA DATA0 nCONFIG VCCA_PLL1 CLK0 LVDSCLK1p Cyclone Device Handbook, Volume 2 CLK1 LVDSCLK1n GNDA_PLL1 GNDG_PLL1 nCEO nCE MSEL0 MSEL1 DCLK IO GND IO PLL1_OUTp IO PLL1_OUTn IO LVDS15p IO LVDS15n IO LVDS14p IO LVDS14n IO LVDS13p IO LVDS13n Altera Corporation May 2003 IO LVDS12p Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 4 of 20) Device Configuration Function VREF Bank VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 B1 B1 VREF2B1 VREF2B1 M5 M4 N1 N2 M6 N7 N5 N6 N3 N4 P5 M2 M3 N7 P7 P2 P1 P6 P5 P3 P4 R1 R2 R6 R5 R3 R4 T4 DQ1L4 DQ1L5 DQS1L DQ1L4 DQ1L5 DQS1L DQ1L1 DQ1L2 DQ1L3 DQ1L1 DQ1L2 DQ1L3 M1 N5 DQ1L0 DQ1L0 L4 N3 L5 N4 L3 N2 L2 N1 L6 N6 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 Package Altera Corporation May 2003 Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA IO LVDS12n IO LVDS11p IO LVDS11n IO LVDS10p IO LVDS10n VCCIO1 GND IO IO LVDS9p IO LVDS9n IO LVDS8p IO LVDS8n IO LVDS7p IO LVDS7n IO LVDS6p IO LVDS6n IO LVDS5p IO LVDS5n IO LVDS4p IO LVDS4n IO LVDS3p IO LVDS3n 5-5 Preliminary Pin List IO DPCLK0 Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 5 of 20) Device Configuration Function VREF Bank VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 B4 B4 VREF2B4 VREF2B4 R4 R5 V6 T6 T7 W6 DQS1B DQS1B T4 U4 T5 U5 V4 U3 T3 T2 V2 V3 W3 Y4 V4 W4 T5 U5 V5 W5 DQ1B7 DQ1B6 DQ1B7 DQ1B6 R3 U3 R2 U2 P4 U4 R1 U1 P3 T3 DQ1L7 P2 T2 DQ1L6 DQ1L6 DQ1L7 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 5-6 Preliminary Package Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA VCCIO1 GND IO LVDS2p IO LVDS2n Cyclone Device Handbook, Volume 2 IO VREF2B1 IO IO LVDS1p IO LVDS1n IO LVDS0p IO LVDS0n IO LVDS128p IO LVDS128n IO LVDS127p IO LVDS127n IO LVDS126p IO LVDS126n IO LVDS125p IO LVDS125n GND VCCIO4 IO DPCLK7 IO VREF2B4 Altera Corporation May 2003 IO LVDS124p Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 6 of 20) Device Configuration Function VREF Bank VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 B4 B4 VREF1B4 VREF1B4 U9 V9 R9 T9 U9 V9 T9 R9 Y9 W9 T10 U10 DM1B DM1B R8 T8 V8 U8 R7 U7 V8 U8 W8 Y8 T7 V7 V7 T8 U7 R7 R6 Y7 DQ1B3 DQ1B2 DQ1B1 DQ1B0 DQ1B3 DQ1B2 DQ1B1 DQ1B0 T6 W7 P7 V6 P6 U6 DQ1B4 U6 Y6 DQ1B5 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 Package Altera Corporation May 2003 Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQ1B5 DQ1B4 DQS for X8 in 400-Pin FineLine BGA IO LVDS124n IO LVDS123p IO LVDS123n IO LVDS122p IO LVDS122n IO LVDS121p IO LVDS121n IO LVDS120p IO LVDS120n IO LVDS119p IO LVDS119n IO LVDS118p IO LVDS118n GND VCCIO4 IO LVDS117p IO LVDS117n IO LVDS116p IO LVDS116n IO LVDS115p IO LVDS115n IO LVDS114p 5-7 Preliminary Pin List IO LVDS114n Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 7 of 20) Device Configuration Function VREF Bank VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF0B4 B4 B4 VREF0B4 VREF0B4 V12 U12 T12 R12 V13 T13 R13 Y13 W13 U13 DQ0B7 DQ0B6 DQ0B5 DQ0B7 DQ0B6 DQ0B5 R11 T11 U11 V11 P10 R10 Y11 R11 Y12 W12 T11 T12 U12 V12 DM0B DM0B T10 W11 V10 U11 U10 V11 Y10 W10 P9 V10 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 5-8 Preliminary Package Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA IO VREF1B4 IO LVDS113p IO LVDS113n GND Cyclone Device Handbook, Volume 2 VCCIO4 IO LVDS112p IO LVDS112n IO LVDS111p IO LVDS111n IO IO LVDS110p IO LVDS110n IO LVDS109p IO LVDS109n IO LVDS108p IO LVDS108n GND VCCIO4 IO LVDS107p IO LVDS107n IO LVDS106p IO LVDS106n Altera Corporation May 2003 IO LVDS105p Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 8 of 20) Device Configuration Function VREF Bank VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 B3 B3 VREF2B3 VREF2B3 T14 R14 V15 U15 U16 T15 T16 T17 T15 T16 W16 V16 V17 U16 Y17 W17 W18 V18 DQ0B3 DQ0B2 DQ0B1 DQ0B0 DQ0B3 DQ0B2 DQ0B1 DQ0B0 U14 P13 P12 U15 Y15 W15 DQS0B DQS0B V15 V14 U14 Y14 W14 R13 T14 T13 R14 U13 V13 DQ0B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 Package Altera Corporation May 2003 Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQ0B4 DQS for X8 in 400-Pin FineLine BGA IO LVDS105n IO LVDS104p IO LVDS104n IO LVDS103p IO LVDS103n IO LVDS102p IO LVDS102n IO LVDS101p IO LVDS101n IO VREF0B4 IO DPCLK6 GND VCCIO4 IO LVDS100p IO LVDS100n IO LVDS99p IO LVDS99n IO LVDS98p IO LVDS98n IO LVDS97p IO LVDS97n IO LVDS96n 5-9 Preliminary Pin List IO LVDS96p Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 9 of 20) Device Configuration Function VREF Bank VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 B3 B3 VREF2B3 VREF2B3 N17 N13 N12 N16 N15 M18 M17 M14 M15 N18 N14 P14 P15 T19 T17 R16 R19 R20 R17 R18 R15 P14 P18 P17 P16 P15 P19 P20 DQ1R3 DQ1R2 DQ1R1 DQ1R3 DQ1R2 DQ1R1 DQS1R DQ1R5 DQ1R4 DQS1R DQ1R5 DQ1R4 P17 T18 P16 U17 DQ1R6 DQ1R6 R16 U19 R15 U18 DQ1R7 R18 U20 DQ1R7 R17 V19 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 5-10 Preliminary Package Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA IO LVDS95n IO LVDS95p IO LVDS94n IO LVDS94p Cyclone Device Handbook, Volume 2 IO VREF2B3 IO GND VCCIO3 IO DPCLK5 IO LVDS93n IO LVDS93p IO LVDS92n IO LVDS92p IO LVDS91n IO LVDS91p IO LVDS90n IO LVDS90p IO LVDS89n IO LVDS89p IO LVDS88n IO LVDS88p IO LVDS87n Altera Corporation May 2003 IO LVDS87p Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 10 of 20) Device Configuration Function VREF Bank VREF2B3 VREF2B3 VREF2B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 B3 B3 VREF1B3 VREF1B3 L14 K16 K15 K17 L12 K18 K14 K13 L15 N15 M18 M17 M15 M16 M20 M19 M14 M13 L13 L18 L17 L19 L16 L20 L16 N16 L13 N20 DM1R DM1R M13 N19 L17 N17 L18 N18 M16 N14 DQ1R0 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 CONF_DONE B3 nSTATUS TCK TMS TDO B3 B3 Package Altera Corporation May 2003 Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQ1R0 DQS for X8 in 400-Pin FineLine BGA IO GND VCCIO3 IO LVDS86n IO LVDS86p IO LVDS85n IO LVDS85p IO LVDS84n IO LVDS84p IO LVDS83n IO LVDS83p IO LVDS82n IO LVDS82p IO LVDS81n IO LVDS81p IO IO PLL2_OUTn IO PLL2_OUTp CONF_DONE nSTATUS TCK TMS 5-11 Preliminary Pin List TDO Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 11 of 20) Device Configuration Function VREF Bank VREF1B3 VREF1B3 B3 B3 VREF1B3 TDI B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 J13 H13 H14 H15 H16 H17 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 J13 K16 K15 J18 J17 J14 H14 J20 J19 J15 J16 H20 H19 H17 H18 DM0R DM0R VREF1B3 J14 K19 VREF1B3 B3 VREF1B3 J17 K18 J12 K17 VREF1B3 J15 L14 VREF1B3 J16 K14 K12 K20 J18 L15 5-12 Preliminary Package Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA GNDG_PLL2 GNDA_PLL2 CLK3 LVDSCLK2n CLK2 LVDSCLK2p Cyclone Device Handbook, Volume 2 VCCA_PLL2 TDI VCCIO3 IO VREF1B3 IO IO LVDS80n IO LVDS80p IO LVDS79n IO LVDS79p IO LVDS78n IO LVDS78p IO LVDS77n IO LVDS77p IO LVDS76n IO LVDS76p IO LVDS75n IO LVDS75p IO LVDS74n Altera Corporation May 2003 IO LVDS74p Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 12 of 20) Device Configuration Function VREF Bank VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 B3 B3 VREF0B3 VREF0B3 E16 E15 D18 F17 E17 D20 DQ0R2 DQ0R1 DQ0R0 DQ0R2 DQ0R1 DQ0R0 F17 F13 F14 F16 F15 E17 F18 F12 G12 G16 G20 G15 G16 F20 F19 F15 F16 E19 E18 F18 DQ0R3 DQS0R DQ0R3 DQS0R G15 G19 G14 G14 G13 H15 G17 G18 G18 G17 DQ0R6 DQ0R5 DQ0R4 H18 H16 DQ0R7 DQ0R7 DQ0R6 DQ0R5 DQ0R4 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 Package Altera Corporation May 2003 Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA GND VCCIO3 IO IO LVDS73n IO LVDS73p IO LVDS72n IO LVDS72p IO LVDS71n IO LVDS71p IO LVDS70n IO LVDS70p IO LVDS69n IO LVDS69p IO LVDS68n IO LVDS68p IO LVDS67n IO LVDS67p IO DPCLK4 GND VCCIO3 IO LVDS66n IO LVDS66p 5-13 Preliminary Pin List IO Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 13 of 20) Device Configuration Function VREF Bank VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 B2 B2 VREF0B2 VREF0B2 B14 C14 E13 C15 D15 B15 A15 E15 F14 A14 B14 DQS0T DQS0T D14 C15 A15 A17 C16 B16 D16 E16 B15 B17 B16 B18 DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ0T0 DQ0T1 DQ0T2 DQ0T3 C16 C17 D17 C18 C17 C19 D15 D18 D16 D19 E14 D17 B3 B3 B3 B3 B3 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 5-14 Preliminary Package Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA IO VREF0B3 IO LVDS65n IO LVDS65p IO LVDS64n Cyclone Device Handbook, Volume 2 IO LVDS64p IO LVDS63n IO LVDS63p IO LVDS62n IO LVDS62p IO LVDS61n IO LVDS61p IO LVDS60n IO LVDS60p VCCIO2 GND IO DPCLK3 IO VREF0B2 IO LVDS59n IO LVDS59p IO LVDS58n IO LVDS58p IO LVDS57n Altera Corporation May 2003 IO LVDS57p Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 14 of 20) Device Configuration Function VREF Bank VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 B2 B2 VREF1B2 VREF1B2 C10 D10 B10 A10 B11 A11 E11 D11 C11 E12 F12 A12 B12 D12 C12 E11 A11 B11 D11 C11 DM0T DM0T A12 D13 B12 C13 C12 B13 D12 A13 C13 D14 DQ0T5 DQ0T6 DQ0T7 D13 C14 DQ0T4 A13 E13 DQ0T4 DQ0T5 DQ0T6 DQ0T7 B13 E14 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 Package Altera Corporation May 2003 Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA IO LVDS56n IO LVDS56p IO LVDS55n IO LVDS55p IO LVDS54n IO LVDS54p IO LVDS53n IO LVDS53p VCCIO2 GND IO LVDS52n IO LVDS52p IO LVDS51n IO LVDS51p IO LVDS50n IO LVDS50p IO IO LVDS49n IO LVDS49p IO LVDS48n IO LVDS48p VCCIO2 5-15 Preliminary Pin List GND Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 15 of 20) Device Configuration Function VREF Bank VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 B2 B2 VREF2B2 VREF2B2 D8 C8 A8 B8 E8 E7 A7 B7 D7 C7 C8 D8 A8 B8 E8 F8 C7 D7 A7 B7 DQ1T0 DQ1T1 DQ1T2 DQ1T3 DQ1T0 DQ1T1 DQ1T2 DQ1T3 B9 A9 C9 D9 A9 B9 D9 C9 E9 DM1T DM1T E10 B10 A10 E10 F10 C10 D10 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 5-16 Preliminary Package Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA IO LVDS47n IO LVDS47p IO VREF1B2 IO LVDS46n Cyclone Device Handbook, Volume 2 IO LVDS46p IO LVDS45n IO LVDS45p IO LVDS44n IO LVDS44p IO LVDS43n IO LVDS43p VCCIO2 GND IO LVDS42n IO LVDS42p IO LVDS41n IO LVDS41p IO LVDS40n IO LVDS40p IO LVDS39n IO LVDS39p IO LVDS38n Altera Corporation May 2003 IO LVDS38p Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 16 of 20) Device Configuration Function VREF Bank VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 A4 B4 B3 C4 A17 A2 B1 B18 F10 F8 G11 D5 C5 B5 C5 D6 D5 A4 B4 B3 C4 A19 A2 B1 B20 H10 H12 J11 DQ1T4 DQ1T5 DQ1T6 DQ1T7 DQ1T4 DQ1T5 DQ1T6 DQ1T7 B5 C6 A6 E6 DQS1T DQS1T C6 B6 B6 A6 D6 F7 E6 E7 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 DEV_OE DEV_CLRn B2 B2 Package Altera Corporation May 2003 Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA IO LVDS37n IO LVDS37p IO LVDS36n IO LVDS36p IO VREF2B2 IO DPCLK2 VCCIO2 GND IO LVDS35n IO LVDS35p IO LVDS34n IO LVDS34p IO LVDS33n IO LVDS33p IO LVDS32n IO LVDS32p VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT 5-17 Preliminary Pin List VCCINT Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 17 of 20) Device Configuration Function VREF Bank G9 H10 J9 K10 L9 M10 M8 N11 N9 U1 U18 V17 V2 N9 W1 W20 Y19 Y2 E1 E1 G7 M7 P1 H8 K8 N8 T1 R10 P11 P8 V14 V5 R12 R8 Y16 Y5 N11 M12 M10 L9 L11 K12 K10 J9 5-18 Preliminary Package Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA VCCINT VCCINT VCCINT VCCINT Cyclone Device Handbook, Volume 2 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO4 VCCIO4 VCCIO4 VCCIO4 Altera Corporation May 2003 VCCIO4 Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 18 of 20) Device Configuration Function VREF Bank E20 E18 H12 M12 P18 A16 A14 A5 E12 E9 A1 A16 A18 A3 B17 B2 C1 C18 F11 F9 G10 G8 H11 F13 F9 A1 A18 A20 A3 B19 B2 C1 C20 G10 G11 G12 G13 G8 F11 A5 T20 N13 K13 H13 Package Altera Corporation May 2003 Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 GND GND GND GND GND GND GND GND GND GND GND GND 5-19 Preliminary Pin List GND Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 19 of 20) Device Configuration Function VREF Bank H8 H9 J10 J11 J8 K11 K8 K9 L10 L11 L8 M11 M9 N10 N8 T1 T18 U17 U2 V1 V16 V18 V3 L12 M11 M9 N10 N12 P10 P11 P12 P13 P8 P9 V1 V20 W19 W2 L10 K9 K11 J12 J10 H9 H11 G9 5-20 Preliminary Package Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA GND GND GND GND Cyclone Device Handbook, Volume 2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Altera Corporation May 2003 GND Table 5-1. Pin List for the Cyclone EP1C20 Device (Part 20 of 20) Device Configuration Function VREF Bank Y1 Y18 Y20 Y3 Package Altera Corporation May 2003 Pin Name / Function Optional Function(s) Bank Number DQS for X8 in 324-Pin 324-Pin 400-Pin FineLine BGA FineLine BGA FineLine BGA DQS for X8 in 400-Pin FineLine BGA GND GND GND GND 5-21 Preliminary Pin List Pin Definitions Table 5-2 shows the pin definitions for the EP1C20 device. 5-22 Preliminary Table 5-2. Pin Definitions for the EP1C20 Device (Part 1 of 4) Pin Description Supply and Reference Pins These are I/O supply voltage pins for banks 1 through 4. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all I/O standards. VCCIO also supplies power to the input buffers used for the LVTTL, LVCMOS, 1.5-V, 1.8-V, 2.5-V, and 3.3-V PCI I/O standards. These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVDS, SSTL2, and SSTL3 I/O standards. Input reference voltage for banks 1-4. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. If voltage reference I/O standards are not used in the bank, the VREF pins are available as user I/O pins. Analog power for PLLs[1..2]. The designer must connect this pin to 1.5 V, even if the PLL is not used. Analog ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board. Guard ring ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board. Pin Name Pin Type (1st, 2nd, & 3rd Function) Cyclone Device Handbook, Volume 2 VCCIO[1..4] Power VCCINT Power VREF[0..2]B[1..4] I/O, Input VCCA_PLL[1..2] Power GNDA_PLL[1..2] Ground GNDG_PLL[1..2] Ground Configuration and JTAG Pins This is a dedicated configuration status pin; it is not available as a user I/O pin. This is a dedicated configuration status pin; it is not available as a user I/O pin. Dedicated configuration control input. A low transition resets the target device; a low-to-high transition begins configuration. All I/O pins tri-state when nCONFIG is driven low. In passive serial configuration mode, DCLK is a clock input used to clock configuration data from an external source into the Cyclone device. In active serial configuration mode, DCLK is a clock output from the Cyclone device (the Cyclone device acts as master in this mode). This is a dedicated pin used for configuration. Dedicated configuration data input pin. CONF_DONE Bidirectional (opendrain) nSTATUS Bidirectional (opendrain) nCONFIG Input DCLK Input (PS mode), Output (AS mode) Altera Corporation May 2003 DATA0 Input Table 5-2. Pin Definitions for the EP1C20 Device (Part 2 of 4) Pin Description Active-low chip enable. Dedicated chip enable input used to detect which device is active in a chain of devices. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Output that drives low when device configuration is complete. During multi-device configuration, this pin feeds a subsequent device's nCE pin. Active serial data output from the Cyclone device. This output pin is utilized during active serial configuration mode. The Cyclone device controls configuration and drives address and control information out on ASDO. In passive serial configuration, this pin is available as a user I/O pin. Chip select output that enables/disables a serial configuration device. This output is utilized during active serial configuration mode. The Cyclone device controls configuration and enables the serial configuration device by driving nCSO low. In passive serial configuration, this pin is available as a user I/O pin. This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, the pin indicates when the device has entered user mode. This pin can be used as a user I/O pin after configuration. Optional user-supplied clock input. Synchronizes the initialization of one or more devices. This pin can be used as a user I/O pin after configuration. Dual-purpose pin that can override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as defined in the design. Dual-purpose pin that can override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design. Dedicated mode select control pins that set the configuration mode for the device. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG output pin. Pin Name Pin Type (1st, 2nd, & 3rd Function) Altera Corporation May 2003 nCE Input nCEO Output ASDO I/O, Output nCSO I/O, Output INIT_DONE I/O, Output (opendrain) CLKUSR I/O, Input DEV_CLRn I/O, Input DEV_OE I/O, Input MSEL[1..0] Input TMS Input TDI Input TCK Input TDO Output Pin Definitions 5-23 Preliminary Table 5-2. Pin Definitions for the EP1C20 Device (Part 3 of 4) Pin Description Clock and PLL Pins Dedicated global clock input. The dual-function of CLK0 is LVDSCLK1p, which is used for differential input to PLL1. Dedicated global clock input. The dual-function of CLK1 is LVDSCLK1n, which is used for differential input to PLL1. Dedicated global clock input. The dual-function of CLK2 is LVDSCLK2p, which is used for differential input to PLL2. Dedicated global clock input. The dual-function of CLK3 is LVDSCLK2n, which is used for differential input to PLL2. Dual-purpose clock pins that can connect to the global clock network. These pins can be used for high fan-out control signals, such as clocks, clears, IRDY, TRDY, or DQS signals. These pins are also available as user I/O pins. External clock output from PLL 1. This pin can be used with differential or single ended I/O standards. If clock output from PLL1 is not used, this pin is available as a user I/O pin. Negative terminal for external clock output from PLL1. If the clock output is single ended, this pin is available as a user I/O pin. External clock output from PLL 2. This pin can be used with differential or single ended I/O standards. If clock output from PLL2 is not used, this pin is available as a user I/O pin. Negative terminal for external clock output from PLL2. If the clock output is single ended, this pin is available as a user I/O pin. 5-24 Preliminary Pin Name Pin Type (1st, 2nd, & 3rd Function) CLK0 Input, LVDS Input CLK1 Input, LVDS Input Cyclone Device Handbook, Volume 2 CLK2 Input, LVDS Input CLK3 Input, LVDS Input DPCLK[7..0] I/O PLL1_OUTp I/O, Output PLL1_OUTn I/O, Output PLL2_OUTp I/O, Output PLL2_OUTn I/O, Output Dual-Purpose LVDS & External Memory Interface Pins LVDS[0..128]p I/O, LVDS RX or TX Dual-purpose LVDS I/O channels 0 to 128. These channels can be used for receiving or transmitting LVDS compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. If not used for LVDS interfacing, these pins are available as user I/O pins. Altera Corporation May 2003 LVDS[0..128]n I/O, LVDS RX or TX Dual-purpose LVDS I/O channels 0 to 128. These channels can be used for receiving or transmitting LVDS compatible signals. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for LVDS interfacing, these pins are available as user I/O pins. Table 5-2. Pin Definitions for the EP1C20 Device (Part 4 of 4) Pin Description Dual-purpose LVDS clock input to PLL1. If differential input to PLL1 is not required, this pin is available as the CLK0 input pin. Dual-purpose LVDS clock input to PLL1. If differential input to PLL1 is not required, this pin is available as the CLK1 input pin. Dual-purpose LVDS clock input to PLL2. If differential input to PLL2 is not required, this pin is available as the CLK2 input pin. Dual-purpose LVDS clock input to PLL2. If differential input to PLL2 is not required, this pin is available as the CLK3 input pin. Optional data strobe signal for use in external memory interfacing. These pins also function as DPCLK pins; therefore, the DQS signals can connect to the global clock network. A programmable delay chain is used to shift the DQS signals by 90 or 72 degrees. Optional data signal for use in external memory interfacing. Optional data mask output signal for use in external memory interfacing. Pin Name Pin Type (1st, 2nd, & 3rd Function) Altera Corporation May 2003 LVDSCLK1p Input, LVDS Input LVDSCLK1n Input, LVDS Input LVDSCLK2p Input, LVDS Input LVDSCLK2n Input, LVDS Input DQS[0..1][L,R,T,B] I/O DQ[0..7][L,R,T,B] I/O DM[0..1][L,R,T,B] I/O Pin Definitions 5-25 Preliminary Cyclone Device Handbook, Volume 2 PLL & Bank Diagram Figure 5-1 shows the PLL and bank locations for the EP1C20 device. Figure 5-1. PLL and Bank Diagram (1), (2) VREF2B2 VREF1B2 VREF0B2 B2 VREF0B1 VREF0B3 VREF1B1 PLL1 PLL2 VREB2B1 B4 VREF2B4 Notes for Figure 5-1: (1) (2) This is a top view of the silicon die. This is a pictoral representation only to get an idea of placement on the device. Refer to the pin-list and the Quartus II software for exact locations. VREF1B4 VREF0B4 5-26 Preliminary Altera Corporation May 2003 VREB2B3 VREF1B3 B1 B3 6. Package Information for Cyclone Devices C52006-1.0 Introduction This data sheet provides package information for Altera(R) devices. It includes these sections: Section Page Device & Package Cross Reference . . . . . . . . . . . . . . . . . . . . . . 6-1 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 In this data sheet, packages are listed in order of ascending pin count. Device & Package Cross Reference Table 6-1 shows which Altera CycloneTM devices are available in FineLine BGA(R) packages. Table 6-1. Cyclone Devices in FineLine BGA Packages Device EP1C4 Package Non-Thermally Enhanced FineLine BGA Non-Thermally Enhanced FineLine BGA Pins 324 400 256 256 324 324 400 EP1C6 EP1C12 Non-Thermally Enhanced FineLine BGA Non-Thermally Enhanced FineLine BGA Non-Thermally Enhanced FineLine BGA EP1C20 Non-Thermally Enhanced FineLine BGA Non-Thermally Enhanced FineLine BGA Altera Corporation May 2003 6-1 Preliminary Cyclone Device Handbook, Volume 2 Thermal Resistance Table 6-2 provides JA (junction-to-ambient thermal resistance) and JC (junction-to-case thermal resistance) values for Altera Cyclone devices. Table 6-2. Thermal Resistance of Cyclone Devices Device EP1C3 Notes (1), (2) JA ( C/W) Still Air 37.5 31.1 28.5 20.7 29.4 27.2 28.7 26.0 24.3 23.0 21.0 20.7 Pin Count 100 144 Package TQFP TQFP FineLine BGA FineLine BGA TQFP PQFP FineLine BGA PQFP FineLine BGA FineLine BGA FineLine BGA FineLine BGA JC ( C/W) 11.0 10.0 8.3 7.9 9.8 4.3 8.8 4.0 6.6 6.1 5.0 4.7 JA ( C/W) 100 ft./min. 35.4 29.4 24.4 17.5 28.0 24.7 24.5 23.4 20.2 19.8 17.7 17.5 JA ( C/W) 200 ft./min. 33.4 27.9 22.1 15.5 26.7 22.1 22.3 20.8 18.1 17.7 15.6 15.5 JA ( C/W) 400 ft./min. 29.8 25.5 20.3 13.9 24.7 17.8 20.5 17.1 16.4 16.1 14.1 13.9 EP1C4 324 400 EP1C6 144 240 256 EP1C12 240 256 324 EP1C20 324 400 Notes to Table 6-2: (1) (2) TQFP: thin quad flat pack PQFP: plastic quad flat pack Package Outlines The package outlines on the following pages are listed in order of ascending pin count. Altera package outlines meet the requirements of JEDEC Publication No. 95. 6-2 Preliminary Altera Corporation May 2003 100-Pin Plastic Thin Quad Flat Pack (TQFP) 100-Pin Plastic Thin Quad Flat Pack (TQFP) All dimensions and tolerances conform to ANSI Y14.5M - 1994. Controlling dimension is in millimeters. N is the number of leads. Package Information Description Ordering Code Reference Package Acronym Lead Material Lead Finish JEDEC Outline JEDEC Option Maximum Lead Coplanarity Weight Moisture Sensitivity Level T TQFP Copper Solder plate (85/15 typical) MS-026 BDE 0.003 inches (0.08 mm) 0.5 g Printed on moisture barrier bag Package Outline Figure Reference Specification Symbol Min. A A1 b D D1 E E1 q 1 2 3 C L L1 R1 R2 S e N 0.08 0.08 0.20 - 0.05 0.17 15.80 13.50 15.80 13.50 0 0 11 11 0.09 0.45 Millimeters Nom. - - 0.22 - - - - 3.5 - 12 12 - 0.60 1.00 REF - - - 0.50 BSC 100 - 0.20 - Max. 1.27 0.15 0.27 16.20 14.50 16.20 14.50 7 - 13 13 0.20 0.75 Altera Corporation 6-3 Preliminary Cyclone Device Handbook, Volume 2 Package Outline D D1 D1 2 D 2 D Detail A 02 Pin 1 E1 2 E1 E A B E 2 03 L1 4X B S L 0 H + 01 R1 R2 B Gage Plane 0.25 A A1 e b C 6-4 Preliminary Altera Corporation 144-Pin Plastic Thin Quad Flat Pack (TQFP) 144-Pin Plastic Thin Quad Flat Pack (TQFP) All dimensions and tolerances conform to ANSI Y14.5M - 1994. Controlling dimension is in millimeters. N is the number of leads. Package Information Description Ordering Code Reference Package Acronym Lead Material Lead Finish JEDEC Outline JEDEC Option Maximum Lead Coplanarity Weight Moisture Sensitivity Level T TQFP Copper Solder plate (85/15 typical) MS-026 BFB 0.003 inches (0.08 mm) 1.3 g Printed on moisture barrier bag Package Outline Figure Reference Specification Symbol Min. A A1 b D D1 e E E1 q 1 2 3 L L1 R1 R2 S N 0.08 0.08 0.20 0 0 11 11 0.45 - 0.05 0.17 Millimeters Nom. - - 0.22 22.00 BSC 20.00 BSC 0.50 BSC 22.00 BSC 20.00 BSC 3.5 - 12 12 0.60 1.00 REF - - - 144 - 0.20 - 7 - 13 13 0.75 Max. 1.60 0.15 0.27 Altera Corporation 6-5 Preliminary Cyclone Device Handbook, Volume 2 Package Outline D D1 D1 2 D D 2 Pin 1 E1 2 Detail A 02 E1 E A B E 2 H + S L 03 L1 B 0 0.25 01 R1 R2 B Gage Plane A A1 e (n-4) X C b 6-6 Preliminary Altera Corporation 240-Pin Plastic Quad Flat Pack (PQFP) 240-Pin Plastic Quad Flat Pack (PQFP) All dimensions and tolerances conform to ANSI Y14.5M - 1994. Controlling dimension is in millimeters. N is the number of leads. Package Information Description Ordering Code Reference Package Acronym Lead Material Lead Finish JEDEC Outline JEDEC Option Maximum Lead Coplanarity Weight Moisture Sensitivity Level Q PQFP Copper Solder plate (85/15 typical) MS-029 GA 0.003 inches (0.08 mm) 7.0 g Printed on moisture barrier bag Package Outline Figure Reference Specification Symbol Min. A A1 A2 D D1 E E1 e b R2 R1 q 1 2 3 L L1 S N 0.17 0.08 0.08 0 0 5 5 0.46 0.40 0.20 - 0.25 3.20 34.35 31.90 34.35 31.90 Millimeters Nom. - - 3.40 - - - - 0.50 BSC - - - 3.5 - - - - - - 240 0.27 0.25 - 8 - 16 16 0.66 - - Max. 4.10 0.50 3.60 34.85 32.10 34.85 32.10 Altera Corporation 6-7 Preliminary Cyclone Device Handbook, Volume 2 Package Outline D D1 D1 2 D D 2 Pin 1 E1 2 E1 E A B E 2 A2 A A1 C (N4)X e b Detail A 02 L1 H + S L 03 B 0 01 R1 R2 B Gage Plane 0.25 6-8 Preliminary Altera Corporation 256-Pin Non-Thermally Enhanced FineLine Ball-Grid Array 256-Pin Non-Thermally Enhanced FineLine Ball-Grid Array All dimensions and tolerances conform to ANSI Y14.5M - 1994. Controlling dimension is in millimeters. M is the maximum solder ball matrix size. Package Information Description Ordering Code Reference Package Acronym Lead Material Lead Finish JEDEC Outline JEDEC Option Maximum Lead Coplanarity Weight Moisture Sensitivity Level F FBGA Tin-lead alloy (63/37) N/A MS-034 AAF-1 0.008 inches (0.20 mm) 1.2 g Printed on moisture barrier bag Package Outline Figure Reference Specification Symbol Min. A (3) A1 A2 A3 D/E b e M 0.50 - 0.30 0.25 - Millimeters Nom. - - - - 17.00 BSC 0.60 1.00 BSC 16 0.70 Max. 3.50 - 1.10 2.50 (3) Altera's thickness specification for A is 2.6 mm maximum. The Max item for A in the table reflects the JEDEC specification. Altera Corporation 6-9 Preliminary Cyclone Device Handbook, Volume 2 Package Outline A D B 16 15 14 13 12 11 10 A 9 8 7 65 4 3 2 1 Pin A1 Indicates location of Pin A1 B C D E F G E H J K L M N P R T A2 A1 A b e C Seating Plane 6-10 Preliminary Altera Corporation 324-Pin Non-Thermally Enhanced FineLine Ball-Grid Array 324-Pin Non-Thermally Enhanced FineLine Ball-Grid Array All dimensions and tolerances conform to ANSI Y14.5M - 1994. Controlling dimension is in millimeters. M is the maximum solder ball matrix size. Package Information Description Ordering Code Reference Package Acronym Lead Material Lead Finish JEDEC Outline JEDEC Option Maximum Lead Coplanarity Weight Moisture Sensitivity Level F FBGA Tin-lead alloy (63/37) N/A MS-034 AAG-1 0.008 inches (0.20 mm) 1.5 g Printed on moisture barrier bag Package Outline Figure Reference Specification Symbol Min. A (4) A1 A2 D/E b e M 0.50 1.20 0.30 0.25 Millimeters Nom. - - - 19.00 BSC 0.60 1.00 BSC 18 0.70 Max. 3.50 - 3.00 (4) Altera's thickness specification for A is 2.6 mm maximum. The Max item for A in the table reflects the JEDEC specification. Altera Corporation 6-11 Preliminary Cyclone Device Handbook, Volume 2 Package Outline A D B A1 Ball Pad Corner 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V Indicates Location of Ball A1 E e b A2 A1 C A Seating Plane 6-12 Preliminary Altera Corporation 400-Pin Non-Thermally Enhanced FineLine Ball-Grid Array 400-Pin Non-Thermally Enhanced FineLine Ball-Grid Array All dimensions and tolerances conform to ANSI Y14.5M - 1994. Controlling dimension is in millimeters. M is the maximum solder ball matrix size. Package Information Description Ordering Code Reference Package Acronym Lead Material Lead Finish JEDEC Outline JEDEC Option Maximum Lead Coplanarity Weight Moisture Sensitivity Level F FBGA Tin-lead alloy (63/37) N/A MS-034 AAJ-1 0.008 inches (0.20 mm) 1.9 g Printed on moisture barrier bag Package Outline Figure Reference Specification Symbol Min. A (5) A1 A2 D/E b (6) e M 0.50 120 0.30 0.25 Millimeters Nom. - - - 21.00 BSC 0.60 1.00 BSC 18 0.70 Max. 3.50 - 3.00 (5) Altera's thickness specification for `A' is 2.6 mm maximum. The Max. dimension for `A' in the table reflects the JEDEC specification. (6) Ball size, parameter `b', can increase to a maximum of 0.74. Contact Altera Applications for more information. Altera Corporation 6-13 Preliminary Cyclone Device Handbook, Volume 2 Package Outline A D B A1 Ball Pad Corner 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y Indicates Location of Ball A1 E e b A A1 A2 6-14 Preliminary Altera Corporation 7. Designing with FineLine BGA Packages C52007-1.0 Introduction As programmable logic devices (PLDs) increase in density and I/O pins, the demand for small packages and diverse packaging options continues to grow. Ball-grid array (BGA) packages are an ideal solution because the I/O connections are on the interior of the device, improving the ratio between pin count and board area. Typical BGA packages contain up to twice as many connections as quad flat pack (QFP) packages for the same area. Further, BGA solder balls are considerably stronger than QFP leads, resulting in robust packages that can tolerate rough handling. Altera has developed a new BGA solution for users of high-density PLDs called the FineLine BGAR package. The new format requires less than half the board space of standard BGA packages. This application note provides guidelines for designing your printed circuit board (PCB) for Altera's FineLine BGA packages and discusses the following topics: Overview of BGA packages PCB layout terminology PCB layout for FineLine BGA packages Overview of BGA Packages As PLDs grow to 1 million gates and beyond, designers require more advanced, flexible packages. BGA packages empower designers by offering the technological benefits and flexibility to meet future system requirements. In BGA packages, the I/O connections are located on the interior of the device. Leads normally placed along the periphery of the package are replaced with solder balls arranged in a matrix across the bottom of the substrate. The final device is soldered directly to the PCB using assembly processes virtually identical to the standard surface mount technology preferred by system designers. In addition, BGA packages provide the following advantages: Fewer damaged leads--BGA leads consist of solid solder balls, which are less likely to suffer damage during handling. More leads per unit area--Lead counts are increased by moving the solder balls closer to the edges of the package and by decreasing the pitch to 1.0 mm. Altera Corporation May 2003 7-1 Preliminary Cyclone Device Handbook, Volume 2 Less expensive surface mount equipment--BGA packages can tolerate slightly imperfect placement during mounting, requiring less expensive surface mount equipment. The placement can be imperfect because the BGA packages self-align during solder reflow. Smaller footprints--BGA packages are usually 20% to 50% smaller than QFP packages, making BGA packages more attractive for applications that require high performance and a smaller footprint. Integrated circuit speed advantages--BGA packages can operate well into the microwave frequency spectrum and can achieve high electrical performance by using ground planes, ground rings, and power rings in the package construction. Improved heat dissipation--Because the die is located at the center of the FineLine BGA package and most VCC and GND pins are located at the center of the package, the GND and VCC pins are located under the die. As a result, the heat generated in the device can be transferred out through the GND and VCC pins (i.e., the GND and VCC pins act as a heat sink). PCB Layout Terminology This section defines common terms used in PCB layout. Escape Routing Escape routing is the method used to route each signal from a package to another element on the PCB. Multi-Layer PCBs The increased I/O count associated with BGA packages has made multi-layer PCBs the industry-standard method for performing escape routing. Signals can be routed to other elements on the PCB through various numbers of PCB layers. Vias Vias, or plated through holes, are used in multi-layer PCBs to transfer signals from one layer to another. Vias are actual holes drilled through a multi-layer PCB and provide electrical connections between various PCB layers. All vias provide layer-to-layer connections only; device leads or other reinforcing material are not inserted into vias. 7-2 Preliminary Altera Corporation May 2003 PCB Layout Terminology Table 7-1 describes the terms used to define via dimensions. Table 7-1. Via Dimension Terms Term Aspect ratio Drilled hole diameter Finished via diameter Definition The aspect ratio is the ratio of a via's length or depth to its pre-plated diameter. The drilled hole diameter is the diameter of the actual via hole drilled in the board. The finished via diameter is the diameter of a via hole that has been finished. Table 7-2 shows the three via types typically used on PCBs. Table 7-2. Via Types Type Through via Description An interconnection between the top and the bottom layer of a PCB. Through vias can also provide interconnections to inner PCB layers. An interconnection from the top or bottom layer to an inner PCB layer. An interconnection between any number of inner PCB layers. Blind via Embedded via Figure 7-1 shows all three via types. Figure 7-1. Types of Vias Through Via Blind Via Embedded Via Connection to Layer PCB Layers Altera Corporation May 2003 7-3 Preliminary Cyclone Device Handbook, Volume 2 Blind vias and through vias are used more frequently than embedded vias. Blind vias can be more expensive than through vias, but overall costs can be reduced because signal traces can be routed under a blind via, requiring fewer PCB layers. Through vias, on the other hand, do not permit signals to be routed through lower layers, which can increase the required number of PCB layers and overall costs. Via Capture Pad Vias are connected electrically to PCB layers through via capture pads, which surround each via. Surface Land Pad Surface land pads are the areas on the PCB to which the BGA solder balls adhere. The size of these pads affects the space available for vias and escape routing. In general, surface land pads are available in the following two basic designs: Non solder mask defined (NSMD), also known as copper defined Solder mask defined (SMD) The main differences between the two surface land pad types are the size of the trace and space, the type of vias you can use, and the shape of the solder balls after solder reflow. Non Solder Mask Defined Pad In the non solder mask defined (NSMD) pad, the solder mask opening is larger than the copper pad. Thus, the surface land pad's copper surface is completely exposed, providing greater area to which the BGA solder ball can adhere (see Figure 7-2). Altera recommends that you use a NSMD pad for most applications because it provides more flexibility, fewer stress points, and more line-routing space between pads. Solder Mask Defined Pad In the solder mask defined (SMD) pad, the solder mask overlaps the surface land pad's copper surface (see Figure 7-2). This overlapping provides greater adhesion strength between the copper pad and the PCB's epoxy/glass laminate, which can be important under extreme bending and during accelerated thermal cycling tests. However, the solder mask overlap shrinks the amount of copper surface available for the BGA solder ball. 7-4 Preliminary Altera Corporation May 2003 PCB Layout Terminology Figure 7-2. Side View of NSMD & SMD Land Pads NSMD Pad SMD Pad Solder Mask Solder Mask Opening Copper Pad Solder Mask Solder Mask Opening Copper Pad PCB Figure 7-3 shows the side view for an NSMD and SMD solder joint. Figure 7-3. Side View of NSMD & SMD Solder Joints NSMD Solder Joint BGA Package BGA Solder Ball Solder Mask PCB Copper Pad SMD Solder Joint Stringer Stringers are rectangular or square interconnect segments that electrically connect via capture pads and surface land pads. Figure 7-4 shows the connection between vias, via capture pads, surface land pads, and stringers. Figure 7-4. Via, Land Pad, Stringer & Via Capture Pad Stringer Via Via Capture Pad Surface Land Pad Altera Corporation May 2003 7-5 Preliminary Cyclone Device Handbook, Volume 2 PCB Layout for FineLine BGA Packages When designing a PCB for FineLine BGA packages, consider the following factors: Surface land pad dimension Via capture pad layout and dimension Signal line space and trace width Number of PCB layers For all FineLine BGA figures, the controlling dimension is millimeters. 1 Surface Land Pad Dimension Surface land pads should be the same size as the BGA pad to provide a balanced stress on solder joints. For this reason, Altera recommends using a 15.75-mil surface land pad, because it is the same size as the BGA pad. Figure 7-5 shows a 15.75-mil BGA pad. Figure 7-5. 15.75-Mil BGA Pad BGA Package BGA Pad BGA Solder Ball 0.40 mm (15.75 mil) 0.63 mm (25.00 mil) Figure 7-6 shows how much space is available for vias and escape routing when you use 15.75-mil surface land pads. 7-6 Preliminary Altera Corporation May 2003 PCB Layout for FineLine BGA Packages Figure 7-6. Space Available for 15.75-Mil Surface Land Pads 1.00 mm (39.37 mil) 0.60 mm (23.62 mil) 0.60 mm (23.62 mil) 0.40 mm (15.75 mil) 1.01 mm (39.76 mil) 1.00 mm (39.37 mil) Surface Land Pads Via Capture Pad Layout & Dimension The size and layout of via capture pads affect the amount of space available for escape routing. In general, you can layout via capture pads in the following two ways: in-line with the surface land pads or in the diagonal of surface land pads. Figure 7-7 shows both layouts. Altera Corporation May 2003 7-7 Preliminary Cyclone Device Handbook, Volume 2 Figure 7-7. Placement of Via Capture Pad In Line Surface land pad Via capture pad Vias 1.00 mm (39.37 mil) 1.00 mm (39.37 mil) Diagonally a Stringer c b a a b c d e f g Stringer length Stringer width Minimum clearance between via capture pad and surface land pad Via capture pad diameter Trace width Space width Area for escape routing (This area is on a different PCB layer than the surface land pads.) b f 0.60 mm (23.62 mil) d 1.00 mm g (39.37 mil) e f d 0.40 mm (15.75 mil) c 0.40 mm (15.75 mil) f e f g The decision to place the via capture pads diagonally or in-line with the surface lands pads is based on the following factors: Diameter of the via capture pad Stringer length Clearance between via capture pad and surface land pad To decide how to lay out your PCB, use the information shown in Figure 7-7 and Table 7-3. If your PCB design guidelines do not conform to either equation in Table 7-3, contact Altera Applications for further assistance. Table 7-3. Formula for Via Layouts Layout In-line Diagonally Formula a + c + d 23.62 mil a + c + d 39.76 mil Table 7-3 shows that you can place a larger via capture pad diagonally than in-line with the surface land pads. 7-8 Preliminary Altera Corporation May 2003 PCB Layout for FineLine BGA Packages Via capture pad size also affects how many traces can be routed on a PCB. Figure 7-8 shows sample layouts of typical and premium via capture pads. The typical layout shows a via capture pad size of 27 mil, a via size of 8 mil, and an inner space/trace of 4 mil. With this layout, only one trace can be routed between the vias. If more traces are required, you must reduce the via capture pad size or the space/trace size. The premium layout shows a via capture pad size of 20 mil, a via size of 5 mil, and an inner space/trace of 3 mil. This layout provides enough space to route two traces between the vias. Figure 7-8. Typical & Premium Via Capture Pad Sizes Typical 39.37 mil Premium 39.37 mil Via Via Capture Pad Space Trace 8.00 mil 27.00 mil 4 mil 5.00 mil 20.00 mil 3 mil 15.00 mil Table 7-4 shows the typical and premium layout specifications used by most PCB vendors. Table 7-4. Vendor Specifications Specification Trace/space width Drilled hole diameter Finished via diameter Via capture pad Aspect ratio Typical (Mil) 5/5 12 8 25.5 7:1 Premium (Mil) 3/3 10 5 20 10:1 f For detailed information on drill sizes, via sizes, space/trace sizes, or via capture pad sizes, contact your PCB vendor directly. Altera Corporation May 2003 7-9 Preliminary Cyclone Device Handbook, Volume 2 Signal Line Space & Trace Width The ability to perform escape routing is defined by the width of the trace and the minimum space required between traces. The minimum area for signal routing is the smallest area that the signal must be routed through (i.e., the distance between two vias, or g in Figure 7-7). This area is calculated by the following formula: g = 39.37 - d The number of traces that can be routed through this area is based on the permitted line trace and space widths. You can use Table 7-5 to determine the total number of traces that can be routed through g. Table 7-5. Number of Traces Number of Traces 1 2 3 Formula g [2 x (space width)] + trace width g [3 x (space width)] + [2 x (trace width)] g [5 x (space width)] + [3 x (trace width)] Figure 7-9 shows that by reducing the trace and space size, you can route more traces through g. Increasing the number of traces reduces the required number of PCB layers and decreases the overall cost. Figure 7-9. Escape Routing for Double & Single Traces Double Trace Routing Single Trace Routing Via Capture Pad 0.12 mm (4.72 mil) 0.40 mm (15.75 mil) 0.60 mm (23.62 mil) 0.40 mm (15.75 mil) 0.40 mm (15.75 mil) 0.20 mm (7.87 mil) 0.40 mm (15.75 mil) 0.60 mm (23.62 mil) Space Trace 7-10 Preliminary Altera Corporation May 2003 PCB Layout for FineLine BGA Packages Number of PCB Layers In general, the number of PCB layers required to route signals is inversely proportional to the number of traces between vias (i.e., the greater the number of traces, the fewer the number of PCB layers required). You can estimate the number of layers your PCB requires by first determining: Trace and space size Number of traces routed between the via capture pads Type of vias used Table 7-6 shows the number of PCB layers required to route signals for various FineLine BGA packages in EPF10K50E devices, assuming the use of a power plane, ground plane, and all I/O pins. This table shows that using double traces and blind vias reduces the required number of layers. Table 7-6. Minimum Required PCB Layers Single Trace FineLine BGA Package (Balls) 100 256 484 672 Double Trace Blind Vias (Layers) 1 2 2 2 Blind Vias (Layers) 2 2 2 3 Through Vias (Layers) 2 2 3 4 Through Vias (Layers) 1 2 2 3 Using fewer I/O pins than the maximum can reduce the required number of layers. Via type can also reduce the number of layers required. To see how the via type can affect the required number of PCB layers, consider the sample layouts shown in Figure 7-10. Altera Corporation May 2003 7-11 Preliminary Cyclone Device Handbook, Volume 2 Figure 7-10. Sample PCB Layout Blind Via The signal from Ball 5 is routed under the via and out the second layer. Ball 5 Ball 4 Ball 3 Ball 2 Ball 1 15.75-mil Surface Land Pad 22-mil Via Capture Pad 8-mil Via 5-mil Trace Through Via The signal from Ball 5 is routed through the via and out the third layer. Ball 5 Ball 4 Ball 3 Ball 2 Ball 1 Signal travels out through first layer Signal travels out through second layer Signal travels out through third layer The blind via layout in Figure 7-10 requires only two PCB layers. The signals from the first two balls can be routed directly through the first layer. The signals from the third and fourth balls can be routed through a via and out the second layer, and the signal from the fifth ball can be routed under the vias for Ball 4 and Ball 3 and out the second layer. Together, only two PCB layers are required. In contrast, the through via layout in Figure 7-10 requires three PCB layers, because signals cannot be routed under through vias. The signals from the third and fourth balls can still be routed through a via and out the second layer, but the signal from the fifth ball must be routed through a via and out the third layer. Using blind vias rather than through vias in this example saves one PCB layer. Conclusion Altera has taken a leadership position in PLD packaging with the recent introduction of 1.00-mm FineLine BGA packages. These packages use a reduced PCB area while maintaining a very high pin count. By using the information in this application note, you can easily design PCBs to use FineLine BGA packages, and take advantage of the package's reduced size. 7-12 Preliminary Altera Corporation May 2003 |
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